8XC196EA USER’S MANUAL

Table 9-3. Port Register Settings for the SSIO Signals

SSIO Signal	Signal Type	Port Register Settings
SC0	Complementary output	P10_DIR.0 = 0
(master, normal transfers)		P10_MODE.0 = 1
SC0	High-impedance input	P10_DIR.0 = 1
(slave, normal transfers)		P10_MODE.0 = 1
		P10_REG.0 = 1
SC0	Open drain with external pull-up	P10_DIR.0 = 1
(master or slave, handshaking transfers)	resistor	P10_MODE.0 = 1
SC1	Open drain with external pull-up	P10_DIR.2 = 1
(master or slave, handshaking transfers)	resistor	P10_MODE.2 = 1
SD0	High-impedance input	P10_DIR.1 = 1
(receiver)		P10_MODE.1 = 1
		P10_REG.1 = 1
SD0	Complementary output	P10_DIR.1 = 0
(transmitter)		P10_MODE.1 = 1
SD1	High-impedance input	P10_DIR.3 = 1
(receiver)		P10_MODE.3 = 1
		P10_REG.3 = 1
SD1	Complementary output	P10_DIR.3 = 0
(transmitter)		P10_MODE.3 = 1
CHS#	High-impedance input	P10_DIR.2 = 1
(master or slave)		P10_MODE.2 = 1
		P10_REG.2 = 1

9.4.2Configuring the SSIO Registers

Use the serial port registers to configure the SSIO port. The SSIO baud register enables the baudrate generator and defines the baud rate for the SSIO baud clock. The SSIO x control register selects the configuration (master or slave, transmitter or receiver) and the transfer type (normal or handshaking) for channel x. The SSIO 0 clock register configures the serial clock for channel 0. The SSIO 1 clock register selects the SSIO mode of operation (standard, duplex, or channel-se- lect), enables the channel-select master contention interrupt request, and configures the serial clock for channel 1. The following sections describe each SSIO register in detail.

9.4.2.1The SSIO Baud (SSIO_BAUD) Register

When an SSIO channel is configured as a master, its serial clock is synchronized with the baud clock during transfers. The SSIO_BAUD register (Figure 9-7) enables the baud-rate generator and defines the baud rate of the baud clock. This register acts as a control register during write operations and as a down-counter monitor during read operations. The frequency ranges from f/8 to f/1024. With a 40-MHz oscillator frequency, this corresponds to a range from a maximum of 5 MHz to a minimum of 39. kHz. Table 9-4 lists SSIO_BAUD values for common baud rates.

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SYNCHRONOUS SERIAL I/O (SSIO) PORT

SSIO_BAUD	Address:	1F94H
	Reset State:	00H

The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the baud rate for the internal baud clock. During read operations, SSIO_BAUD serves as the down-counter monitor. The down-counter is decremented once every four state times when the baud-rate generator is enabled.

7

0

BE

BV6

BV5

BV4

BV3

BV2

BV1

BV0

Bit

Bit

Function

Number

Mnemonic

7

BE

Baud-rate Generator Enable

This bit enables and disables the baud-rate generator.

For write operations:

0 = disable the baud-rate generator and clear BV6:0

1 = enable the baud-rate generator and start the down-counter

For read operations:

0 = baud-rate generator is disabled

1 = baud-rate generator is enabled and down-counter is running

6:0

BV6:0

Baud Value

For write operations:

These bits represent baud value, an unsigned integer that determines

the baud rate. The maximum value of baud value is 7FH; the minimum

value is 0. Use the following equation to determine baud value for a

given baud rate.

Baud Value

f

1

= ------------------------------------- –

Baud Rate × 8

For read operations:

These bits contain the current value of the down-counter.

Figure 9-7. Synchronous Serial Port Baud (SSIO_BAUD) Register

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8XC196EA USER’S MANUAL

Table 9-4. Common SSIO_BAUD Values at 40 MHz Operating Frequency

	Baud Rate	SSIO_BAUD Value†
(Maximum)	5.0 MHz	80H
	100.0 KHz	B1H
	50.0 KHz	D3H
	40.0 KHz	FCH
(Minimum)	39.1 KHz	FFH

†Bit 7 must be set to enable the baud-rate generator.

9.4.2.2The SSIO Control (SSIOx_CON) Register

The SSIOx_CON register (Figure 9-8) selects the channel configuration (master or slave, transmitter or receiver), data transfer type (normal or handshaking), and indicates buffer status. SSIOx_CON also determines whether the SSIO re-enables the channel at the completion of a transfer.

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SYNCHRONOUS SERIAL I/O (SSIO) PORT

SSIOx_CON	Address:	1F91H, 1F93H
x = 0–1	Reset State:	00H

The synchronous serial control x (SSIOx_CON) register selects the channel configuration (master or slave, transmitter or receiver), the data transfer type (normal or handshaking), and indicates buffer status. SSIOx_CON also determines whether the SSIO re-enables the channel at the completion of a transfer.

7

0

M/S#

T/R#

TRT

THS

STE

ATR

OUF

TBS

Bit

Bit

Function

Number

Mnemonic

7

M/S#

Master/Slave Select

Configures the channel as either master or slave.

0 = slave (externally generated clocking signal is input on SCx)

1 = master (internally generated clocking signal is output on SCx)

In standard mode, either channel can act as master or slave. In channel-

select and duplex modes, configure channel 1 as a slave (SSIO1_CON.7

= 0) and configure channel 0 as desired.

6

T/R#

Transmit/Receive Select

Configures the channel as either transmitter or receiver.

0 = receiver (data is input on SDx)

1 = transmitter (data is output on SDx)

In standard mode, either channel can act as transmitter or receiver. In

channel-select and duplex modes, configure channel 0 as the transmitter

(SSIO0_CON.6 = 1) and channel 1 as the receiver (SSIO0_CON.6 = 0).

5

TRT

Transmitter/Receiver Toggle

Setting this bit causes the SSIO to toggle the channel configuration

(transmitter or receiver) at the completion of a transfer, thus avoiding

possible contention on the data line. The SSIO clears this bit at the

completion of each transfer.

4

THS

Transceiver Handshake Select

Selects the type of data transfer.

0 = normal transfers (all modes)

1 = handshaking transfers (standard mode)

In standard mode, the channels can perform either normal or

handshaking transfers. In channel-select and duplex modes, always

configure the channels for normal transfers by clearing this bit.

Set STE and ATR, along with THS, for handshaking transfers.

Figure 9-8. Synchronous Serial Control x (SSIOx_CON) Registers

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8XC196EA USER’S MANUAL

SSIOx_CON (Continued)	Address:	1F91H, 1F93H
x = 0–1	Reset State:	00H

The synchronous serial control x (SSIOx_CON) register selects the channel configuration (master or slave, transmitter or receiver), the data transfer type (normal or handshaking), and indicates buffer status. SSIOx_CON also determines whether the SSIO re-enables the channel at the completion of a transfer.

7

0

M/S#

T/R#

TRT

THS

STE

ATR

OUF

TBS

Bit

Bit

Function

Number

Mnemonic

3

STE

Single Transfer Enable

Enables and disables transfer of a single byte. Unless ATR is set, STE is

automatically cleared at the end of a transfer.

0

= disable transfer

1

= enable transfer

Set THS, STE, and ATR for handshaking transfers.

2

ATR

Automatic Transfer Re-enable

Enables and disables subsequent transfers.

0

= disable subsequent transfers (allow automatic clearing of STE)

1

= enable subsequent transfers (prevent automatic clearing of STE)

Set THS, STE, and ATR for handshaking transfers.

1

OUF

Overflow/Underflow Flag

Indicates whether an overflow or underflow has occurred. An attempt to

access SSIOx_BUF during a byte transfer sets this bit.

For the master (M/S# = 1)

0

= no overflow or underflow has occurred

1

= the core attempted to access SSIOx_BUF during the current transfer

For the slave (M/S# = 0)

0

= no overflow or underflow has occurred

1

= the core attempted to access SSIOx_BUF during the current transfer

or the master attempted to clock data into or out of the slave’s

SSIOx_BUF before the buffer was available

0

TBS

Transceiver Buffer Status

Indicates the status of the channel’s SSIOx_BUF.

For transmissions (T/R# =1)

0

=

SSIOx_BUF is full; waiting to transmit

1

= SSIOx_BUF is empty; buffer available

For receptions (T/R# = 0)

0

= SSIOx_BUF is empty; waiting to receive

1

=

SSIOx_BUF is full; data available

Figure 9-8. Synchronous Serial Control x (SSIOx_CON) Registers (Continued)

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