8XC196EA USER’S MANUAL

4

3

2

1

39

Execution

Ending

"NORML"

End

Vector to PTS

PTS

PTS

Instruction

"NORML"

Control Block

Interrupt

PTS Interrupt Routine

Interrupt Pending Bit

Set

Cleared

Response Time

Latency Time

43 State Times

A0142-02

Figure 6-7. PTS Interrupt Response Time

Table 6-6. Execution Times for PTS Cycles

PTS Mode

Execution Time (in State Times)

Single transfer mode

register/register†

22 per byte or word transfer + 1

memory/register†

25 per byte or word transfer + 1

memory/memory†

28 per byte or word transfer + 1

Block transfer mode

register/register†

14 + 8 per byte or word transfer (1 minimum)

memory/register†

17 + 8 per byte or word transfer (1 minimum)

memory/memory†

20 + 8 per byte or word transfer (1 minimum)

Dummy mode

13

Missed-event mode

27

†Register indicates an access to the register file or a peripheral SFR. Memory indicates an access to a memory-mapped register, I/O, or memory. See Table 6-4 on page 6-7 for address information.

6.5PROGRAMMING THE INTERRUPTS

Table 6-7 describes how to program each maskable interrupt.

6-18

STANDARD AND PTS INTERRUPTS

Table 6-7. Programming the Interrupts

To perform this function:	Your code must:
Enable interrupt controller service for the	Execute the EI instruction.
maskable interrupts
Disable interrupt controller service for the	Execute the DI instruction.
maskable interrupts, including the end-
of-PTS interrupts
Enable PTS service for the maskable	Execute the EPTS instruction.
interrupts (Notes 1, 2)
Disable PTS service for the maskable	Execute the DPTS instruction.
interrupts
Disable an individual maskable interrupt	Clear the interrupt’s mask bit in the INT_MASK or INT_MASK1
	register (Figure 6-8 or 6-9).
Disable a PIH interrupt source	Clear the interrupt’s mask bit in the PIHx_INT_MASK register
	(Figure 6-10 or 6-11).
Enable a maskable interrupt for standard	Set the interrupt’s mask bit in the INT_MASK or INT_MASK1
interrupt service (Note 3)	register (Figure 6-8 or 6-9) and clear its PTS select bit (Figure
	6-12).
Enable a maskable interrupt for PTS	Set the interrupt’s mask bit in the INT_MASK or INT_MASK1
interrupt service	register (Figure 6-8 or 6-9) and set its PTS select bit (Figure
	6-12).
Enable a PIH interrupt for standard	First enable the PIH interrupt source and select standard
interrupt service	interrupt service:
	Set the interrupt’s mask bit in the PIHx_INT_MASK register
	(Figure 6-10 or 6-11) and clear its PTS select bit in the
	PIHx_PTSSEL register (Figure 6-12).
	Then enable the PIHx_INT interrupt request:
	Set its mask bit in the INT_MASK or INT_MASK1 register
	(Figure 6-8 or 6-9) and clear its PTS select bit (Figure 6-12).
Enable a PIH interrupt for PTS interrupt	First enable the PIH interrupt source and select PTS interrupt
service	service:
	Set the interrupt’s mask bit in the PIHx_INT_MASK register
	(Figure 6-10 or 6-11) and set its PTS select bit in the
	PIHx_PTSSEL register (Figure 6-12).
	Then enable the PIHx_PTS interrupt:
	Set its mask bit in the INT_MASK or INT_MASK1 register
	(Figure 6-8 or 6-9) and set its PTS select bit (Figure 6-12).

NOTES:

1.When you assign an interrupt to the PTS, you must set up a PTS control block (PTSCB) for each interrupt source (see “Initializing the PTS Control Blocks” on page 6-30).

2.PTS service is not useful for shared interrupts because the PTS cannot readily determine the source of these interrupts.

3.Never select standard interrupt service for the PIHx_PTS interrupt. If you do, the interrupt controller will try to service the PIHx_PTS interrupt. If no normal interrupts are pending in the PIH, the PIH responds with a dummy interrupt and does not clear the PTS interrupt pending bit. The PIH will continue to request service, causing an infinite loop.

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8XC196EA USER’S MANUAL

INT_MASK	Address:	0008H
	Reset State:	00H

The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register. Interrupt calls cannot occur immediately following a push instruction. POPF or POPA restores it.

7										0
SDU	EXTINT		RI1	TI1			AD	EPAx_OVR	RI0	TI0
Bit						Function
Number
7:0	Setting a bit enables the corresponding interrupt.
	Bit Mnemonic Interrupt Description
	SDU		Serial Debug Unit lnterrupt
	EXTINT		External Interrupt Pin
	RI1		SIO1 Receive
	TI1		SIO1 Transmit
	AD		A/D Conversion Complete
	EPAx_OVR		EPA Channel 3–16 Overrun
	RI0		SIO0 Receive
	TI0		SIO0 Transmit

Figure 6-8. Interrupt Mask (INT_MASK) Register

6-20

STANDARD AND PTS INTERRUPTS

INT_MASK1	Address:	0013H
	Reset State:	00H

The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.

7

0

NMI

STACK

PIH0_PTS

PIH0_INT

PIH1_PTS

PIH1_INT

SSIO1

SSIO0

Bit

Function

Number

7:0

Setting a bit enables the corresponding interrupt.

Bit Mnemonic

Interrupt Description

NMI†

Nonmaskable Interrupt

STACK†

Stack Overflow Error

PIH0_PTS

PIH0 PTS Service Request

PIH0_INT

PIH0 Interrupt Request

PIH1_PTS

PIH1 PTS Service Request

PIH1_INT

PIH1 Interrupt Request

SSIO1

SSIO1 Transfer

SSIO0

SSIO0 Transfer

† The NMI and stack overflow interrupts are always enabled. These nonfunctional mask

bits exist for design symmetry with the INT_PEND1 register. Always write zeros to these

bits.

Figure 6-9. Interrupt Mask 1 (INT_MASK1) Register

PIH0_INT_MASK

Address:

1E98H

Reset State:

0000H

The PIH0 interrupt mask (PIH0_INT_MASK) register enables or disables (masks) individual interrupt requests to peripheral interrupt handler 0. (The EI and DI instructions enable and disable servicing of all maskable interrupts.)

15									8
EPA15	EPA14		EPA13	EPA12		EPA11	EPA10	EPA9	EPA8
7									0
EPA7	EPA6		EPA5	EPA4		EPA3	EPA2	EPA1	EPA0
Bit						Function
Number
15:0	Setting a bit enables the corresponding interrupt request to peripheral interrupt handler 0.
	Bit Mnemonic Interrupt Description
	EPA15:0		EPA Capture/Compare Channels 0–15

Figure 6-10. PIH0 Interrupt Mask (PIH0_INT_MASK) Register

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8XC196EA USER’S MANUAL

PIH1_INT_MASK	Address:	1EA8H
	Reset State:	0000H

The PIH1 interrupt mask (PIH1_INT_MASK) register enables or disables (masks) individual interrupt requests to the peripheral interrupt handler 1. (The EI and DI instructions enable and disable servicing of all maskable interrupts.)

15										8
EPA16	OS7	OS6		OS5		OS4		OS3	OS2	OS1
7										0
OS0	OVRTM1	OVRTM2		OVRTM3		OVRTM4		OVR0	OVR1	OVR2
Bit						Function
Number
15:0	Setting a bit enables the corresponding interrupt request to peripheral interrupt handler 1.
	Bit Mnemonic		Interrupt Description
	EPA16		EPA Capture/Compare Channel 16
	OS7:0		Output Simulcapture Channel 0–7
	OVRTM1:4		Timer 1–4 Overflow/Underflow
	OVR0:2		EPA Channel 0–2 Capture Overrun

Figure 6-11. PIH1 Interrupt Mask (PIH1_INT_MASK) Register

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STANDARD AND PTS INTERRUPTS

PTSSEL	Address:	0004H
	Reset State:	0000H

The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware clears the corresponding PTSSEL bit when PTSCOUNT reaches zero. The end-of-PTS interrupt service routine must reset the PTSSEL bit to re-enable the PTS channel.

15

—	—	PIH0_PTS	0
7
SDU	EXTINT	RI1	TI1

8

PIH1_PTS	0	SSIO1	SSIO0
			0
AD	EPAx_OVR	RI0	TI0

Bit		Function
Number
15, 14	Reserved; for compatibility with future devices, write zeros to these bits.
12, 10	To guarantee proper device operation, write zeros to these bits.
13, 11,	Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine.
9:0	The PTS interrupt vector locations are as follows:
	Bit Mnemonic	Interrupt	PTS Vector
	PIH0_PTS†	PIH0 PTS Service Request	see PIH0_PTSSEL
	PIH1_PTS†	PIH1 PTS Service Request	see PIH1_PTSSEL
	SSIO1	SSIO 1 Transfer	FF2052H
	SSIO0	SSIO 0 Transfer	FF2050H
	SDU	Serial Debug Unit lnterrupt	FF204EH
	EXTINT	External Interrupt Pin	FF204CH
	RI1	SIO1 Receive	FF204AH
	TI1	SIO1 Transmit	FF2048H
	AD	A/D Conversion Complete	FF2046H
	EPAx_OVR	EPA Channel 3–16 Overrun	FF2044H
	RI0	SIO0 Receive	FF2042H
	TI0	SIO0 Transmit	FF2040H
	† Unless these interrupts are masked in the INT_MASK1 register, always write ones to
	these bits.

Figure 6-12. PTS Select (PTSSEL) Register

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8XC196EA USER’S MANUAL

PIH0_PTSSEL	Address:	1E96H
	Reset State:	0000H

The PTS select (PIH0_PTSSEL) register for the peripheral interrupt handler 0 selects either a PTS service request or a standard interrupt service request for the corresponding interrupt. Setting a bit selects a PTS service request; clearing a bit selects a standard interrupt service request. In PTS modes that use the PTSCOUNT register, hardware clears the corresponding bit in both the PIH0_PTSSEL and PTSSEL registers when PTSCOUNT reaches zero. The end-of-PTS interrupt service routine must reset the PIH0_PTSSEL bit to re-enable the PTS channel.

15

EPA15	EPA14	EPA13	EPA12
7
EPA7	EPA6	EPA5	EPA4

8

EPA11	EPA10	EPA9	EPA8
			0
EPA3	EPA2	EPA1	EPA0

Bit

Function

Number

15:0 Setting a bit causes the peripheral interrupt handler 0 (PIH0) to generate the PIH0_PTS interrupt request when the corresponding interrupt is generated and enabled.

The PTS interrupt vector locations are as follows:

Bit Mnemonic	Interrupt	PTS Vector
EPA15	EPA Capture/Compare Channel 15	FF20FEH
EPA14	EPA Capture/Compare Channel 14	FF20FAH
EPA13	EPA Capture/Compare Channel 13	FF20F6H
EPA12	EPA Capture/Compare Channel 12	FF20F2H
EPA11	EPA Capture/Compare Channel 11	FF20EEH
EPA10	EPA Capture/Compare Channel 10	FF20EAH
EPA9	EPA Capture/Compare Channel 9	FF20E6H
EPA8	EPA Capture/Compare Channel 8	FF20E2H
EPA7	EPA Capture/Compare Channel 7	FF20DEH
EPA6	EPA Capture/Compare Channel 6	FF20DAH
EPA5	EPA Capture/Compare Channel 5	FF20D6H
EPA4	EPA Capture/Compare Channel 4	FF20D2H
EPA3	EPA Capture/Compare Channel 3	FF20CEH
EPA2	EPA Capture/Compare Channel 2	FF20CAH
EPA1	EPA Capture/Compare Channel 1	FF20C6H
EPA0	EPA Capture/Compare Channel 0	FF20C2H

Figure 6-13. PIH0 PTS Select (PIH0_PTSSEL) Register

6-24