MEMORY PARTITIONS

The 8XC196EA features a stack overflow module, which monitors the stack pointer and generates a nonmaskable interrupt if it crosses the upper or lower boundary you have specified. Refer to Chapter 5, “Stack Overflow Module,” for details.

4.2.5.3CPU Special-function Registers (SFRs)

Locations 0000–0017H in the lower register file are the CPU SFRs (Table 4-6). Appendix C describes the CPU SFRs.

Table 4-6. CPU SFRs

Address	High (Odd) Byte	Low (Even) Byte
0016H	Reserved	Reserved
0014H		WSR
0012H	INT_MASK1	INT_PEND1
0010H	Reserved	Reserved
000EH	Reserved	Reserved
000CH	Reserved	Reserved
000AH	Reserved	WATCHDOG
0008H	INT_PEND	INT_MASK
0006H	PTSSRV (H)	PTSSRV (L)
0004H	PTSSEL (H)	PTSSEL (L)
0002H	ONES_REG (H)	ONES_REG (L)
0000H	ZERO_REG (H)	ZERO_REG (L)

4.3WINDOWING

Windowing expands the amount of memory that is accessible with direct addressing. Direct addressing can access the lower register file with short, fast-executing instructions. With windowing, direct addressing can also access the upper register file and peripheral SFRs.

NOTE

Memory-mapped SFRs must be accessed using indirect or indexed addressing modes; they cannot be windowed. Reading a memory-mapped SFR through a window returns FFH (all ones). Writing to a memory-mapped SFR through a window has no effect.

Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The 8XC196EA has two window selection registers, WSR and WSR1. WSR selects a 32-, 64-, or 128-byte segment of higher memory to be windowed into the top of the lower register file space. WSR1 selects a 32or 64-byte segment of higher memory to be mapped into the middle of the lower register file.

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8XC196EA USER’S MANUAL

Because the areas in the lower register file do not overlap, two windows can be in effect at the same time. This allows you to directly address a block of peripheral SFRs in one window and a block of register RAM in another. For example, you can activate a 128-byte window using WSR and a 64-byte window using WSR1 (Figure 4-5). These two windows occupy locations 0040– 00FFH in the lower register file, leaving locations 001A–003FH for use as general-purpose register RAM, locations 0018–0019H for the stack pointer or general-purpose register RAM, and locations 0000–0017H for the CPU SFRs.

	03FFH	128-byte Window
	0380H	(WSR = 17H)
	037FH	64-byte Window
	0340H	(WSR1 = 2DH)
	00FFH
		WSR Window in
	0080H	Lower Register File
	007FH	WSR1 Window in
	0040H	Lower Register File
	003FH
	0000H

A3239-01

Figure 4-5. Windowing

4.3.1Selecting a Window

The window selection register (Figure 4-6) has two functions. The HLDEN bit (WSR.7) enables and disables the bus-hold protocol (see Chapter 15, “Interfacing with External Memory”); it is unrelated to windowing. The remaining bits select a window to be mapped into the top of the lower register file. Table 4-7 on page 4-20 provides a quick reference of WSR values for windowing the peripheral SFRs. Table 4-8 on page 4-21 lists the WSR values for windowing the upper register file.

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MEMORY PARTITIONS

WSR	Address:	0014H
	Reset State:	00H

The window selection register (WSR) has two functions. One bit enables and disables the bus-hold protocol. The remaining bits select windows. Windows map sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it.

0

HLDEN

W6

W5

W4

W3

W2

W1

W0

Bit

Bit

Function

Number

Mnemonic

7

HLDEN

HOLD#, HLDA# Protocol Enable

This bit enables and disables the bus-hold protocol (see Chapter 15, “Inter-

facing with External Memory”). It has no effect on windowing.

0 = disable

1 = enable

6:0

W6:0

Window Selection

These bits specify the window size and number. See Table 4-7 on page

4-20 for peripheral SFR windows or Table 4-8 on page 4-21 for upper

register file windows.

Figure 4-6. Window Selection (WSR) Register

WSR1

Address:

0015H

Reset State:

00H

Window selection 1 (WSR1) register selects a 32or 64-byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register file.

NOTE: The PUSHA and POPA instructions do not save and restore WSR1.
											0
	W6	W5	W4		W3		W2		W1		W0
Bit	Bit				Function
Number	Mnemonic
7	—	Reserved; for compatibility with future devices, write zero to this bit.
6:0	W6:0	Window Selection
		These bits specify the window size and number. See Table 4-7 on page
		4-20 for peripheral SFR windows or Table 4-8 on page 4-21 for upper
		register file windows.

Figure 4-7. Window Selection 1 (WSR1) Register

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8XC196EA USER’S MANUAL

Table 4-7. Selecting a Window of Peripheral SFRs

			WSR or WSR1	WSR or WSR1
		SFR	Value for 32-byte	Value for 64-byte	WSR Value for
	Peripherals	Locations	Window	Window	128-byte Window
		(Hex)	(00E0–00FFH or	(00C0–00FFH or	(0080–00FFH)
			0060–007FH)	0040–007FH)
	Ports 3–5, 12, EPORT,
	memory access control†	1FE0–1FFF†	†
	Ports 2, 7, 8, 9, 10	1FC0–1FDF	7EH	3FH†
	Port 11, reset source	1FA0–1FBF	7DH
	SIO, SSIO	1F80–1F9F	7CH	3EH	1FH†
	Timers, clockout control	1F60–1F7F	7BH
	EPA0–7	1F40–1F5F	7AH	3DH
	EPA8–15	1F20–1F3F	79H	3CH
	EPA16	1F00–1F1F	78H		1EH
	OS0–7	1EE0–1EFF	77H
	PWM	1EC0–1EDF	76H	3BH
	PIH1	1EA0–1EBF	75H
	Chip-select 1 & 2, PIH0	1E80–1E9F	74H	3AH	1DH
	Chip-select 0, A/D	1E60–1E7F
	control, A/D 8–15 result		73H
	A/D 0–7 result	1E40–1E5F	72H	39H	1CH

†Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through windows. Reading these locations through a window returns FFH; writing these locations through a window has no effect. Memory-mapped SFRs must be accessed with indirect or indexed addressing.

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