STANDARD AND PTS INTERRUPTS

PIH1_PTSSEL	Address:	1EA6H
	Reset State:	0000H

The PTS select register for the peripheral interrupt handler 1 (PIH1_PTSSEL) selects either a PTS service request or a standard interrupt service request for the corresponding interrupt. Setting a bit selects a PTS service request; clearing a bit selects a standard interrupt service request. In PTS modes that use the PTSCOUNT register, hardware clears the corresponding bit in both the PIH1_PTSSEL and PTSSEL registers when PTSCOUNT reaches zero. The end-of-PTS interrupt service routine must reset the PIH1_PTSSEL bit to re-enable the PTS channel.

15

EPA16	OS7	OS6	OS5
7
OS0	OVRTM1	OVRTM2	OVRTM3

8

OS4	OS3	OS2	OS1
			0
OVRTM4	OVR0	OVR1	OVR2

Bit

Function

Number

15:0 Setting a bit causes the peripheral interrupt handler 1(PIH1) to generate the PIH1_PTS interrupt request when the corresponding interrupt is generated and enabled.

The PTS interrupt vector locations are as follows:

Bit Mnemonic	Interrupt	PTS Vector
EPA16	EPA Capture/Compare Channel 16	FF213EH
OS7	Output Simulcapture Channel 7	FF213AH
OS6	Output Simulcapture Channel 6	FF2136H
OS5	Output Simulcapture Channel 5	FF2132H
OS4	Output Simulcapture Channel 4	FF212EH
OS3	Output Simulcapture Channel 3	FF212AH
OS2	Output Simulcapture Channel 2	FF2126H
OS1	Output Simulcapture Channel 1	FF2122H
OS0	Output Simulcapture Channel 0	FF211EH
OVRTM1	Timer 1 Overflow/Underflow	FF211AH
OVRTM2	Timer 2 Overflow/Underflow	FF2116H
OVRTM3	Timer 3 Overflow/Underflow	FF2112H
OVRTM4	Timer 4 Overflow/Underflow	FF210EH
OVR0	EPA Channel 0 Capture Overrun	FF210AH
OVR1	EPA Channel 1 Capture Overrun	FF2106H
OVR2	EPA Channel 2 Capture Overrun	FF2102H

Figure 6-14. PIH1 PTS Select (PIH1_PTSSEL) Register

6.5.1Modifying Interrupt Priorities

Your software can modify the default priorities of maskable interrupts by controlling the interrupt mask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts, if any, can interrupt an interrupt service routine. The following code shows one way to prevent all interrupts, except EXTINT (priority 6), from interrupting an SIO1 receive interrupt (RI1) service routine (priority 5).

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8XC196EA USER’S MANUAL

SERIAL_RI1_ISR:
PUSHA	; Save PSW, INT_MASK, INT_MASK1, & WSR.
	; No interrupts acknowledged until after next
	; instruction
LDB INT_MASK, #01000000B ; Enable EXTINT only
EI	; Enable interrupt servicing
	; Service the RI1 interrupt
POPA	; Restore PSW, INT_MASK, INT_MASK1, & WSR
RET
CSEG AT 0FF200AH	; fill in interrupt table
DCW LSW SERIAL_RI1_IS	; LSW is a compiler directive that means
	; least-significant word of vector address
END

Note that location FF200AH in the interrupt vector table must be loaded with the value of the label SERIAL_RI1_ISR before the interrupt request occurs and that the interrupt must be enabled for this routine to execute.

This routine, like all interrupt service routines, is handled in the following manner:

1.After the hardware detects and prioritizes an interrupt request, it generates and executes an interrupt call. This pushes the program counter onto the stack and then loads it with the contents of the vector corresponding to the highest priority, pending, unmasked interrupt. The hardware will not allow another interrupt call until after the first instruction of the interrupt service routine is executed.

2.The PUSHA instruction saves the contents of the PSW, INT_MASK, INT_MASK1, and window selection register (WSR) onto the stack and then clears the PSW, INT_MASK, and INT_MASK1 registers. In addition to the arithmetic flags, the PSW contains the global interrupt enable bit (I) and the PTS enable bit (PSE). By clearing the PSW and the interrupt mask registers, PUSHA effectively masks all maskable interrupts, disables standard interrupt servicing, and disables the PTS. Because PUSHA is a protected instruction, it also inhibits interrupt calls until after the next instruction executes.

3.The LDB INT_MASK1 instruction enables those interrupts that you choose to allow to interrupt the service routine. In this example, only EXTINT can interrupt the receive interrupt service routine. By enabling or disabling interrupts, the software establishes its own interrupt servicing priorities.

4.The EI instruction re-enables interrupt processing and inhibits interrupt calls until after the next instruction executes.

5.The actual interrupt service routine executes within the priority structure established by the software.

6.At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.

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STANDARD AND PTS INTERRUPTS

Notice that the “preamble” and exit code for this routine do not save or restore register RAM. The interrupt service routine is assumed to allocate its own private set of registers from the lower register file. The general-purpose register RAM in the lower register file makes this quite practical. In addition, the RAM in the upper register file is available via windowing (see “Windowing” on page 4-17).

6.5.2Determining the Source of an Interrupt

When hardware detects an interrupt, it sets the corresponding bit in the INT_PEND or INT_PEND1 register (Figures 6-15 or 6-16). It sets the bit even if the individual interrupt is disabled (masked). Software can read INT_PEND and INT_PEND1 to determine which interrupts are pending. If a PIH interrupt request (PIHx_INT or PIHx_PTS) is pending, software can read the PIHx_INT_PEND register (Figure 6-17 or 6-18) to determine the source of the interrupt request.

When the CPU acknowledges an interrupt request, hardware clears the bit in the INT_PEND or INT_PEND1 register.

Software can generate an interrupt by setting a bit in the INT_PEND or INT_PEND1 register. Use the read-modify-write instructions, such as AND and OR, to modify these registers.

ANDB INT_PEND, #11111110B; Clears the TI0 pending bit ORB INT_PEND, #00000001B; Sets the TI0 pending bit

Other methods could result in a partial interrupt cycle. For example, an interrupt could occur during an instruction sequence that loads the contents of the interrupt pending register into a temporary register, modifies the contents of the temporary register, and then writes the contents of the temporary register back into the interrupt pending register. If the interrupt occurs during one of the last four states of the second instruction, it will not be acknowledged until after the completion of the third instruction. Because the third instruction overwrites the contents of the interrupt pending register, the interrupt will not be acknowledged.

If software clears the pending bit in the PIHx_INT_PEND register while the shared interrupt pending bit is still set, the CPU will try to service the interrupt. When this occurs, the PIH responds with a dummy interrupt vector address (2014H for standard interrupts and 2016H for PTS interrupts). Initialize FF2014H to point to a simple routine that contains only a RET instruction, and initialize FF2016H to point to address 0000H (see “Dummy Mode” on page 6-40).

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8XC196EA USER’S MANUAL

INT_PEND	Address:	0009H
	Reset State:	00H

When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

7											0
SDU	EXTINT		RI1	TI1			AD	EPAx_OVR	RI0		TI0
Bit						Function
Number
7:0	Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared
	when processing transfers to the corresponding interrupt vector.
	Bit Mnemonic Interrupt Description
	SDU		Serial Debug Unit lnterrupt
	EXTINT		External Interrupt Pin
	RI1		SIO1 Receive
	TI1		SIO1 Transmit
	AD		A/D Conversion Complete
	EPAx_OVR		EPA Channel 3–16 Overrun†
	RI0		SIO0 Receive
	TI0		SIO0 Transmit
	† It is not possible to determine which EPA channel caused the EPAx_OVR interrupt
	request.

Figure 6-15. Interrupt Pending (INT_PEND) Register

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STANDARD AND PTS INTERRUPTS

INT_PEND1	Address:	0012H
	Reset State:	00H

When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

7

0

NMI

STACK

PIH0_PTS

PIH0_INT

PIH1_PTS

PIH1_INT

SSIO1

SSIO0

Bit

Function

Number

7:0

Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared

when processing transfers to the corresponding interrupt vector.

Bit Mnemonic

Interrupt Description

NMI

Nonmaskable Interrupt

STACK

Stack Overflow Error

PIH0_PTS

PIH0 PTS Service Request

PIH0_INT

PIH0 Interrupt Request

PIH1_PTS

PIH1 PTS Service Request

PIH1_INT

PIH1 Interrupt Request

SSIO1

SSIO1 Transfer

SSIO0

SSIO0 Transfer

Figure 6-16. Interrupt Pending 1 (INT_PEND1) Register

PIH0_INT_PEND

Address:

1E9AH

Reset State:

0000H

When the peripheral interrupt handler 0 detects an interrupt request, it sets the corresponding bit in the interrupt pending (PIH0_INT_PEND) register. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

15								8
EPA15	EPA14	EPA13	EPA12		EPA11	EPA10	EPA9	EPA8
7								0
EPA7	EPA6	EPA5	EPA4		EPA3	EPA2	EPA1	EPA0
Bit					Function
Number
15:0	Any set bit indicates that the corresponding PIH0 interrupt is pending. The interrupt bit is
	cleared when processing transfers to the corresponding interrupt vector.
	Bit Mnemonic Interrupt Description
	EPA15:0	EPA Capture/Compare Channels 0–15

Figure 6-17. PIH0 Interrupt Pending (PIH0_INT_PEND) Register

6-29