EVENT PROCESSOR ARRAY (EPA)

11.4 EPA CHANNEL FUNCTIONAL OVERVIEW

The EPA has both programmable capture/compare and specialized compare-only channels. Each capture/compare channel can perform the following tasks. (The compare-only channels have the same functionality except that they cannot capture an external event. In addition, the compareonly channels can capture the value of a timer when they generate an output event.)

•capture the current timer value when a specified transition occurs on the EPA pin

•start an A/D conversion when an event is captured or when the timer value matches the programmed value in the event-time register

•clear, set, or toggle the EPA pin when the timer value matches the programmed value in the event-time register

•generate an interrupt when a capture or compare event occurs

•generate an interrupt when a capture overrun occurs

Each EPA channel has a control register, EPAx_CON; an event-time register, EPAx_TIME; and a timer/counter input (Figure 11-4). The control register selects the timer, the mode, and either the event that causes a timer/counter value to be captured or the event that is to occur at a given timer/counter value. The event-time register holds the captured timer value in capture mode or the event time in compare mode. See “Programming the Timers” on page 11-15 for configuration information.

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8XC196EA USER’S MANUAL
External Clocking		Timer/Counter Unit
(TxCLK)		TIMER4
		TIMER3
Internal Clocking		TIMER2
		TIMER1
				EPA Capture/Compare
		Capture Overrun		Channel x
OVRx
Interrupt			Capture	EPA Pin
	EPAx_TIME
			Buffer
			Compare	TGL
Bus
EPA
Interrupt				Reset Timer
	EPAx_CON	Overwrite		Start A/D
		Mode Control		Mode Selection
		Concatenate
				A4330-01
	Figure 11-4. A Single EPA Capture/Compare Channel

11.4.1 Operating in Input Capture Mode

In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register, which sets the EPA interrupt pending bit as shown in Figure 11-5. If enabled, an interrupt is generated. If a second event occurs before the CPU reads the first timer value in EPAx_TIME, the second timer value is loaded into the buffer and held there. After the CPU reads the EPAx_TIME register, the value from the capture buffer is automatically transferred into EPAx_TIME and the EPA interrupt pending bit is set again.

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EVENT PROCESSOR ARRAY (EPA)

TIMERx

Event Occurs

at EPA Pin

Capture Buffer

EPA

Interrupt

Pending Bit

Set

EPAx_TIME

Read-out Time Value

A2458-02

Figure 11-5. EPA Simplified Input Capture Structure

If a third event occurs before the CPU reads the event-time register, the overwrite bit (EPAx_CON.1) determines how the EPA will handle the event. If the bit is clear, the EPA ignores the third event. If the bit is set, the third event time overwrites the second event time in the capture buffer. Table 11-3 summarizes the possible actions when a valid event occurs.

NOTE

For an event to be captured, the signal must be stable for at least two state times both before and after the transition occurs (Figure 11-6).

Event 1
	2 State		2 State
	Times		Times
Event 2
	2 State		2 State
	Times		Times

A3130-01

Figure 11-6. Valid EPA Input Events

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8XC196EA USER’S MANUAL

		Table 11-3. Action Taken When a Valid Edge Occurs
	Overwrite Bit	Status of
		Capture Buffer	Action Taken When a Valid Edge Occurs
	(EPAx_CON.1)
		& EPAx_TIME
	0	empty	Edge is captured and event time is loaded into the capture buffer and
			EPAx_TIME register.
	0	full	New data is ignored — no capture, EPA interrupt, or transfer occurs.
	1	empty	Edge is captured and event time is loaded into the capture buffer and
			EPAx_TIME register.
	1	full	Old data is overwritten in the capture buffer.

An input capture event does not set the interrupt pending bit until the captured time value actually moves from the capture buffer into the EPAx_TIME register. If the buffer contains data and the PTS is used to service the interrupts, then two PTS interrupt requests will occur almost back-to- back (that is, with one instruction executed between the interrupts).

11.4.2 Operating in Output Compare Mode

When the selected timer value matches the event-time value, the action specified in the control register occurs (i.e., no output occurs or the pin is set, cleared, or toggled, or an A/D conversion is initiated). If the re-enable bit (EPAx_CON.5) is set, the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoccur until a new value is written to the eventtime register. See “Programming the Capture/Compare Channels” on page 11-19 for configuration information.

11.4.3 Operating in Compare Mode with the Output/Simulcapture Channels

When the selected timer value matches the event-time value, the action specified in the control register occurs (i.e., the pin is set, cleared, or toggled, or an A/D conversion is initiated, or the waveform generator is reloaded), and the value of the selected timer is captured. If the re-enable bit (OSx_CON.5) is set, the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoccur until a new value is written to the event-time register. See “Programming the Timers” on page 11-15 and “Programming the Capture/Compare Channels” on page 11-19 for configuration information.

11.4.4 Generating a 32-bit Time Value

The 83C196EA’s EPA module enables you to concatenate a pair of timers and a pair of EPA channels to generate or capture a 32-bit time value. Figure 11-7 illustrates this configuration using timers 1 and 2 and EPA channels 1 and 0. You can use timers 3 and 4 and any pair of adjacent channels in this same manner.

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