8XC196EA USER’S MANUAL

Table 17-1. Signal Descriptions (Continued)

	Port	Special-function	Typ	Mode	Description
	Pin	Signal	e
	P1.2:1,	PBUS	I/O	ROM-dump	Address/Command/Data Bus
	P4.5:0,				During ROM-dump, these pins serve as a regular
	P3.7:0
					system bus to access external memory. Leave P4.7:6
					unconnected and connect P1.2:1 to serve as the
					upper address signals.
	P5.4	TMODE#	I	All	Test-mode Entry Pins
	P5.3	RD#	I/O		To enter serial port mode, ROM-dump, or SDU RISM
	P5.0	ALE	I/O
					execution routine, you must hold four pins low during
	PLLEN	—	I
					reset: P5.4, P5.3, P5.0, and PLLEN† .
	P2.0	TXD0	O		The remaining test-mode entry pins (P2.0, P2.6, and
	P2.6	HLDA#/ONCE#	I
					P5.2) must be high during reset. Because these pins
	P5.2	WR#/WRL#	I/O
					have weak pull-ups internally, they will be in the
					correct state during reset. You need only ensure that
					your system does not drive these pins low.
					† PLLEN=0 disables the clock doubler, so the
					maximum frequency in test-ROM mode is FXTAL1.

	Table 17-2. Control and Status Register
Mnemonic	Description
CCR0	Chip Configuration 0 Register
	The chip configuration 0 (CCR0) register controls ROM access, enables or disables
	idle and powerdown modes, and selects the write-control mode. It also contains the
	bus-control parameters for fetching chip configuration byte 1.

17.2 MEMORY PROTECTION OPTIONS

The lock bit in chip configuration register 0 (CCR0) controls access to the ROM. Clearing CCB0.7 enables read protection. With read protection enabled, the bus controller will not read from protected areas of ROM. An attempt to read the ROM when the slave program counter contains an external address always returns F0FDH. Because the slave program counter can be as much as eight bytes ahead of the CPU program counter, the bus controller might prevent code execution from the last eight bytes of internal memory. The interrupt vectors and CCBs are not read protected because interrupts can occur even when executing from external memory. Figure 17-1 describes CCB0.

17-2

USING THE TEST-ROM ROUTINES

CCR0	no direct access†

The chip configuration 0 (CCR0) register controls ROM access, enables or disables idle and powerdown modes, and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.

7

0

LOC

1

WS1

WS0

DEMUX

BHE#

BW16

PD

Bit

Bit

Function

Number

Mnemonic

7

LOC

Lock Bit

This bit controls read access to the ROM during normal operation.

0

= read protect

1

= no protection

Refer to “Controlling Read Access to the Internal ROM” on page 4-26 for

details.

6

1

To guarantee proper operation, write one to this bit.

5:4

WS1:0

Wait States

These bits, along with the READY pin, control the number of wait states

that are used for an external fetch of chip configuration byte 1 (CCB1).

WS1 WS0

0

0

zero wait states

0

1

one wait state

1

0

two wait states

1

1

three wait states

If READY is low when this number is reached, additional wait states are

added until READY is pulled high.

3

DEMUX

Select Demultiplexed Bus

Selects the demultiplexed bus mode for an external fetch of CCB1:

0

= multiplexed — address and data are multiplexed on AD15:0.

1

= demultiplexed — data only on AD15:0.

2

BHE#

Write-control Mode

Selects the write-control mode, which determines the functions of the

BHE#/WRH# and WR#/WRL# pins for external bus cycles:

0

= write strobe mode: the BHE#/WRH# pin operates as WRH#, and the

WR#/WRL# pin operates as WRL#.

1

= standard write-control mode: the BHE#/WRH# pin operates as

BHE#, and the WR#/WRL# pin operates as WR#.

1

BW16

Buswidth Control

Selects the bus width for an external fetch of CCB1:

0

= 8-bit bus

1

= 16-bit bus

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1

Figure 17-1. Chip Configuration 0 (CCR0) Register

17-3

8XC196EA USER’S MANUAL

CCR0 (Continued) no direct access†

The chip configuration 0 (CCR0) register controls ROM access, enables or disables idle and powerdown modes, and selects the write-control mode. It also contains the bus-control parameters for fetching chip configuration byte 1.

7										0
LOC	1		WS1	WS0		DEMUX	BHE#	BW16		PD
Bit	Bit					Function
Number	Mnemonic
0	PD		Powerdown Enable
			Enables or disables the IDLPD #1 and IDLPD #2 instructions. When
			enabled, the IDLPD #1 instruction causes the microcontroller to enter idle
			mode and the IDLPD #2 instruction causes the microcontroller to enter
			powerdown mode.0 = disable idle and powerdownmodes
			1 = enable idle and powerdown modes
			If your design uses idle or powerdown mode, set this bit when you
			program the CCBs. If it does not, clearing this bit when you program the
			CCBs will prevent accidental entry into idle or powerdown mode.
			(Chapter 14, “Special Operating Modes,” discusses idle and powerdown
			modes.)

† The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1

Figure 17-1. Chip Configuration 0 (CCR0) Register (Continued)

NOTE

The developers have made a substantial effort to provide an adequate program protection scheme. However, Intel cannot and does not guarantee that these protection methods will always prevent unauthorized access.

17-4