8XC196EA USER’S MANUAL

15.9 SYSTEM BUS AC TIMING SPECIFICATIONS

Refer to the latest datasheet for the AC timings to ensure your system meets specifications. The major external bus timing specifications are shown in Figures 15-19 and 15-20.

	TCLCL
	t	TCHDV
	TCLLH	TRLCL	TCHCL
CLKOUT	TLLCH		TRHLH
		TLHLH
			TLHLL
		TLLRL
ALE
		TRLRH
		TRLAZ	TRHDZ
RD#
		TRLDV
	TAVLL	TLLAX
AD15:0		TAVDV
	Address Out		Data In
(read)
			TCHWH
		TLLWL
			TWHLH
		TWLWH	TWHQX

WR#

	AD15:0		TQVWH
		Address Out	Data Out	Address Out
	(write)
				TWHBX, TRHBX

BHE#, INST

TWHAX, TRHAX

AD15:8	High Address Out
A20:16	Extended Address Out

TWHSH, TRHSH

CSx#

A3252-01

Figure 15-19. Multiplexed System Bus Timing

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INTERFACING WITH EXTERNAL MEMORY

TCHCL	TCLCL	t
TCLLH		TCHWH
CLKOUT	TLHLH
		TWHLH
	TLLCH	TRHLH	TLHLL
ALE
		TRHRL
		TRHDZ
TAVRL	TRLRH	TRHAX
RD#
	TCHDV
	TRLDV
	TAVDV
AD15:0	TSLDV
		Data In
(read)
	TWLCL	TWHQX
TAVWL		TWHAX
	TWLWH
WR#
AD15:0	TQVWH
	Data Out
(write)
		TWHBX, TRHBX
BHE#, INST
A20:0	Address Out
CSx#
			A3255-02

Figure 15-20. Demultiplexed System Bus Timing

15.9.1 Deferred Bus-cycle Mode

The microcontroller offers a deferred bus-cycle mode. This bus mode (enabled by CCR1.5; see Figure 15-7 on page 15-19) reduces bus contention when using the microcontroller in demultiplexed mode with slow memories. As shown in Figure 15-21, a delay of 2t occurs in the first bus cycle following a chip-select output change or the first write cycle following a read cycle.

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8XC196EA USER’S MANUAL
CLKOUT
	TLHLH + 2t	T	WHLH	+ 2t
ALE
	TRHLH + 2t
		TAVRL + 2t
RD#
			TAVDV+ 2t
AD15:0	Data In			Data In
(read)		TAVWL + 2t
WR#
AD15:0	Data Out	Data Out		Data Out
(write)
BHE#, INST
A20:0	Address Out	Valid		Valid
CSx#
				A3246-02

Figure 15-21. Deferred Bus-cycle Mode Timing Diagram

15.9.2 Explanation of AC Symbols

Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. For example, TLLRL is the time between signal L (ALE) condition L (Low), and signal R (RD#) condition L (Low). Table 15-11 defines the signal and condition codes.

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	INTERFACING WITH EXTERNAL MEMORY
	Table 15-11. AC Timing Symbol Definitions
A	AD15:0, A20:0
B	BHE#
C	CLKOUT
D	AD15:0, AD7:0, SDx (SSIO input data)
H	HOLD#
HA	HLDA#
L	ALE
Q	AD15:0, AD7:0, SDx (SSIO output data)
R	RD#
S	CSx#
W	WR#, WRL#
Character	Condition
H	High
L	Low
V	Valid
X	No Longer Valid
Z	Floating (low impedance)

15.9.3 AC Timing Definitions

Tables 15-12 and 15-13 define the AC timing specifications that the memory system must meet and those that the microcontroller will provide.

	Table 15-12. External Memory Systems Must Meet These Specifications
Symbol		Definition
TAVDV		Address Valid to Input Data Valid
		Maximum time the memory device has to output valid data after the microcontroller outputs a
		valid address.
T		CLKOUT† High to Input Data Valid
CHDV
		Maximum time the memory system has to output valid data after CLKOUT rises.
TQVWH		Data Valid to WR# High
		Time between data being valid on the bus and the microcontroller deasserting WR#.
TRHDZ		RD# High to Input Data Float
		Time after RD# is inactive until the memory system must float the bus. If this timing is not met,
		bus contention will occur.

† Assumes CLKOUT is equal to twice the internal operating period (2t).

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8XC196EA USER’S MANUAL

Table 15-12. External Memory Systems Must Meet These Specifications (Continued)

Symbol	Definition
TRLDV	RD# Low to Input Data Valid
	Maximum time the memory system has to output valid data after the microcontroller asserts
	RD#.

† Assumes CLKOUT is equal to twice the internal operating period (2t).

Table 15-13. The Microcontroller Meets These Specifications

fOperating frequency

Frequency of the signal input on the XTAL1 pin times the clock multiplier (x); x is 1 or 2 depending on the clock mode. The internal bus speed of the microcontroller is f/2.

t	Operating period (1/f)
	All AC Timings are referenced to t.
TAVLL	Address Setup to ALE Low
	Length of time the address is valid before ALE falls. Use this specification when designing the
	external latch.
TAVRL	Address Setup to RD# Low
	Length of time the address is valid before RD# falls.
TAVWL	Address Setup to WR# Low
	Length of time the address is valid before WR# falls.
T	CLKOUT† High Period
CHCL
	Needed in systems that use CLKOUT as clock for external devices.
T	CLKOUT† High to WR# High
CHWH
	Time between CLKOUT going high and WR# going inactive.
T	CLKOUT† Cycle Time
CLCL
	Normally 2t.
T	CLKOUT† Falling to ALE Rising
CLLH
	Use to derive other timings.
TLHLH	ALE Cycle Time
	Minimum time between ALE pulses.
TLHLL	ALE High Period
	Use this specification when designing the external latch.
TLLAX	Address Hold after ALE Low
	Length of time the address is valid after ALE falls. Use this specification when designing the
	external latch.
T	ALE Falling to CLKOUT† Rising
LLCH
	Use to derive other timings.

† Assumes CLKOUT is equal to twice the internal operating period (2t).

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INTERFACING WITH EXTERNAL MEMORY

	Table 15-13. The Microcontroller Meets These Specifications (Continued)
TLLRL		ALE Low to RD# Low
		Length of time after ALE falls before RD# is asserted. Could be needed to ensure proper
		memory decoding takes place before a device is enabled.
TLLWL		ALE Low to WR# Low
		Length of time after ALE falls before WR# is asserted. Could be needed to ensure proper
		memory decoding takes place before a device is enabled.
TRHAX		(Multiplexed Mode) AD15:8/CSx# Hold after RD# High
		Minimum time that the high byte of the address in 8-bit mode will be valid after RD# inactive.
		(Demultiplexed Mode) A20:0/CSx# Hold after RD# High
		Minimum time that the address will be valid after RD# inactive.
TRHBX		BHE#, INST Hold after RD# High
		Minimum time that these signals will be valid after RD# inactive.
TRHLH		RD# High to ALE Rising
		Time between the microcontroller deasserting RD# and the next ALE. Useful in calculating time
		between RD# inactive and next address valid.
TRLAZ		RD# Low to Address Float
		Used to calculate when the microcontroller stops driving the address on the bus.
T		RD# Low to CLKOUT† Low
RLCL
		Length of time from RD# asserted to CLKOUT falling edge.
TRLRH		RD# Low to RD# High
		RD# pulse width.
TWHAX		(Multiplexed Mode) AD15:8/CSx# Hold after WR# High
		Minimum time that the high byte of the address in 8-bit mode will be valid after WR# inactive.
		(Demultiplexed Mode) A20:0/CSx# Hold after WR# High
		Minimum time that the address will be valid after WR# inactive.
TWHBX		BHE#, INST Hold after WR# High
		Minimum time that these signals will be valid after WR# inactive.
TWHLH		WR# High to ALE High
		Time between the microcontroller deasserting WR# and next ALE. Also used to calculate WR#
		inactive and next Address valid.
TWHQX		Data Hold after WR# High
		Minimum time after WR# rises that the data stays valid on the bus.
TWHSH		A20:0/CSx# Hold after WR# High
		Minimum time that the address and chip-select output are held after WR# inactive.
T		WR# Low to CLKOUT† Low
WLCL
		Minimum and maximum time between WR# being asserted and CLKOUT going low.
TWLWH		WR# Low to WR# High
		WR# pulse width.

† Assumes CLKOUT is equal to twice the internal operating period (2t).

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Serial Debug Unit