8XC196EA USER’S MANUAL

Once the A/D converter receives the command to start a conversion, a delay time elapses before sampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediate conversions, those initiated directly by a write to AD_COMMAND, begin within three state times after the instruction is completed.) During this sample delay, the hardware clears the successive approximation register and selects the designated multiplexer channel. After the sample delay, the device connects the multiplexer output to the sample capacitor for the specified sample time. After this sample window closes, the microcontroller disconnects the multiplexer output from the sample capacitor so that changes on the input pin will not alter the stored charge while the conversion is in progress. The device then zeros the comparator and begins the conversion.

The A/D converter uses a successive approximation algorithm to perform the analog-to-digital conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process. The resistive ladder provides 20 mV steps (VREF = 5.12 volts), while capacitive coupling creates 5 mV steps within the 20 mV ladder voltages. Therefore, 1024 internal reference voltage levels are available for comparison against the analog input to generate a 10-bit conversion result. In 8- bit conversion mode, only the resistive ladder is used, providing 256 internal reference voltage levels.

The successive approximation conversion compares a sequence of reference voltages to the analog input, performing a binary search for the reference voltage that most closely matches the input. The ½ full scale reference voltage is the first tested. This corresponds to a 10-bit result where the most-significant bit is zero and all other bits are ones (0111111111B). If the analog input was less than the test voltage, bit 9 of the SAR is left at zero, and a new test voltage of ¼ full scale (0011111111B) is tried. If the analog input was greater than the test voltage, bit 8 of SAR is set. Bit 7 is then cleared for the next test (0101111111B). This binary search continues until 10 (or 8) tests have occurred, at which time the valid conversion result resides in the AD_RESULT and AD_RESULTx registers, where it can be read by software. The result is equal to the ratio of the input voltage divided by the analog supply voltage. If the ratio is 1.00, the result will be all ones.

12.4 PROGRAMMING THE A/D CONVERTER

The following A/D converter parameters are programmable:

•conversion input — input channel

•conversion times — sample window time and conversion time for each bit

•operating mode — 8- or 10-bit conversion or 8-bit high or low threshold detection

•conversion trigger — immediate or EPA starts

This section describes the A/D converter’s registers and explains how to program them.

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ANALOG-TO-DIGITAL (A/D) CONVERTER

12.4.1 Programming the A/D Test Register

The AD_TEST register (Figure 12-2) selects either the analog input specified in AD_COMMAND or a test voltage (ANGND or VREF) for conversion and specifies an offset voltage to be applied to the resistor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on VREF. With the results of these conversions, use a software routine to calculate the zero-offset error. Specify the zero-offset adjustment by writing the appropriate value to AD_TEST. This offset voltage is added to the resistor ladder and applies to all input channels. “Understanding A/D Conversion Errors” on page 12-17 describes zero-offset and other errors inherent in A/D conversions.

AD_TEST	Address:	1E76H
	Reset State:	00H

The A/D test (AD_TEST) register enables conversions on ANGND and VREF and specifies adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND and one on VREF. With these results, a software routine can calculate the offset and gain errors.

7											0
—	—		—		OFF2		OFF1		OFF0	TV	TE
Bit	Bit						Function
Number	Mnemonic
7:5	—		Reserved; for compatibility with future devices, write zeros to these bits.
4:2	OFF2:0		Offset
			These bits allow you to set the zero-offset point.
			OFF2 OFF1 OFF0
			0	0	0		no adjustment
			0	0	1		add 2.5 mV
			0	1	0		subtract 2.5 mV
			0	1	1		subtract 5.0 mV
			1	0	0		no adjustment
			1	0	1		add 5.0 mV
			1	1	0		subtract 7.5 mV
			1	1	1		subtract 10 mV

Figure 12-2. A/D Test (AD_TEST) Register

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8XC196EA USER’S MANUAL

AD_TEST(Continued)	Address:	1E76H
	Reset State:	00H

The A/D test (AD_TEST) register enables conversions on ANGND and VREF and specifies adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND and one on VREF. With these results, a software routine can calculate the offset and gain errors.

7										0
—	—		—		OFF2		OFF1	OFF0	TV	TE
Bit	Bit						Function
Number	Mnemonic
1	TV		Test Voltage
			This bit selects the test voltage for a test mode conversion. (The TE bit
			must be set to enable test mode.)
			0	= ANGND
			1	= VREF
0	TE		Test Enable
			This bit determines whether normal or test mode conversions will be
			performed. A normal conversion converts the analog signal input on one
			of the analog input channels. A test conversion allows you to perform a
			conversion on ANGND or VREF, selected by the TV bit.
			0	= normal
			1	= test

Figure 12-2. A/D Test (AD_TEST) Register (Continued)

12.4.2 Programming the A/D Result Register (for Threshold Detection Only)

To use the threshold-detection modes, you must first write a value to the high byte of AD_RESULT (Figure 12-3) to set the desired reference (threshold) voltage.

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ANALOG-TO-DIGITAL (A/D) CONVERTER

AD_RESULT (Write)	Address:	1E72H
	Reset State:	0000H

The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes.

15											8
REFV7	REFV6		REFV5		REFV4		REFV3	REFV2	REFV1		REFV0
7											0
—	—			—	—		—	—	—		—
Bit	Bit						Function
Number	Mnemonic
15:8	REFV7:0			Reference Voltage
				These bits specify the threshold value. This reference voltage is
				compared with an analog input pin. When the voltage on the analog
				input pin crosses over (detect high) or under (detect low) the threshold
				value, the A/D conversion complete interrupt pending bit is set.
				Use the following formula to determine the value to write to this register
				for a given threshold voltage.
				reference voltage = desired threshold voltage × 256----------------------------------------------------------------------------------
							VREF –	ANGND
7:0	—			Reserved; for compatibility with future devices, write zeros to these bits.

Figure 12-3. A/D Result (AD_RESULT) Register — Write Format

12.4.3 Programming the A/D Time Register

Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy.

The AD_TIME register (Figure 12-4) specifies the A/D sample and conversion times. To avoid erroneous conversion results, use the TSAM and TCONV specifications in the datasheet to determine appropriate values.

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8XC196EA USER’S MANUAL

AD_TIME	Address:	1E77H
	Reset State:	FFH

The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. This register programs the speed at which the A/D can run — not the speed at which it can convert correctly. Consult the data sheet for recommended values. Initialize the AD_TIME register before initializing the AD_COMMAND register. Do not write to this register while a conversion is in progress; the results are unpredictable.

7

0

SAM2

SAM1

SAM0

CONV4

CONV3

CONV2

CONV1

CONV0

Bit

Bit

Function

Number

Mnemonic

7:5

SAM2:0

A/D Sample Time

These bits specify the sample time. Use the following formula to

compute the sample time.

SAM =

TSAM × f –

2

-------------------------------

8

where:

SAM

=

1 to 7

TSAM

= the sample time, in μs, from the data sheet

f

= the internal operating frequency, in MHz

4:0

CONV4:0

A/D Bit Conversion Time

These bits specify the conversion time for each bit. Use the following

formula to compute the conversion time.

CONV =

TCONV

× f – 3

– 1

----------------------------------

where:

2 × B

CONV=

2 to 31

TCONV

= the conversion time, in μs, from the data sheet

f

= the internal operating frequency, in MHz

B

= the number of bits to be converted (8 or 10)

Figure 12-4. A/D Time (AD_TIME) Register

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