INTERFACING WITH EXTERNAL MEMORY

15.7 BUS-HOLD PROTOCOL

The microcontroller supports a bus-hold protocol that allows external devices to gain control of the address/data bus. The protocol uses three signals: HOLD#/P2.5 (bus-hold request), HLDA#/P2.6 (bus-hold acknowledge), and BREQ#/P5.4 (bus request).

When an external device wants to use the microcontroller bus, it asserts the HOLD# signal. The microcontroller samples HOLD# while CLKOUT is low. If HOLD# is asserted, the microcontroller responds by releasing the bus and asserting HLDA#. During this hold time, the address/data bus floats, and signals CSx#, ALE, RD#, WR#/WRL#, BHE#/WRH#, and INST are weakly held in their inactive states. Figure 15-15 shows the timing for the bus-hold protocol, and Table 15-8 lists the timing parameters and their definitions. Consult the datasheet for timing diagrams and specifications.

When the external device is finished with the bus, it relinquishes control by driving HOLD# high. In response, the microcontroller deasserts HLDA# and resumes control of the bus.

If the microcontroller has a pending external bus cycle while another device has control of the bus, it asserts BREQ# to request control of the bus. After the external device responds by releasing HOLD#, the microcontroller exits hold and then deasserts BREQ# and HLDA#.

CLKOUT
T	THVCH
HVCH
HOLD#	Hold Latency
TCLHAL	TCLHAH
HLDA#
TCLBRL	TCLBRH
BREQ#
THALAZ	THAHAX
A20:0, AD15:0
THALBZ	T
CSx#, BHE#,	HAHBV
INST, RD#, WR#	Weakly held inactive
WRL#, WRH#	TCLLH
ALE
	Start of strongly driven ALE
	A3287-01
Figure 15-15. HOLD#, HLDA# Timing

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8XC196EA USER’S MANUAL

Table 15-8. HOLD#, HLDA# Timing Definitions

Symbol	Parameter
THVCH	HOLD# Setup Time
T	CLKOUT† Low to HLDA# Low
CLHAL
T	CLKOUT† Low to HLDA# High
CLHAH
T	CLKOUT† Low to BREQ# Low
CLBRL
T	CLKOUT† Low to BREQ# High
CLBRH
THALAZ	HLDA# Low to Address Float
THAHAX	HLDA# High to Address No Longer Float
THALBZ	HLDA# Low to CSx#, BHE#, INST, RD#, WR#, WRL#,
	WRH# Weakly Driven
THAHBV	HLDA# High to CSx#, BHE#, INST, RD#, WR#, WRL#,
	WRH# valid
TCLLH	Clock Falling to ALE Rising

† Assumes CLKOUT is equal to twice the internal operating period (2t).

When the external device is finished with the bus, it relinquishes control by driving HOLD# high. In response, the microcontroller deasserts HLDA# and resumes control of the bus.

If the microcontroller has a pending external bus cycle while another device has control of the bus, it asserts BREQ# to request control of the bus. After the external device responds by releasing HOLD#, the microcontroller exits hold and then deasserts BREQ# and HLDA#.

15.7.1 Enabling the Bus-hold Protocol

To use the bus-hold protocol, first configure P2.5/HOLD#, P2.6/HLDA#, and P5.4/BREQ# as special-function signals. (BREQ# and HLDA# are active-low outputs; HOLD# is an active-low input.) To enable the bus-hold protocol, set WSR.7. Once WSR.7 is set, an attempt to reconfigure HOLD#, BREQ#, or HLDA# to serve as a general-purpose I/O signal is ignored until the bushold protocol is disabled (that is, until you clear WSR.7 or reset the microcontroller).

15.7.2 Disabling the Bus-hold Protocol

To disable hold requests, clear WSR.7. The microcontroller does not take control of the bus immediately after WSR.7 is cleared. Instead, it waits for the current hold request to finish and then disables the bus-hold feature and ignores any new requests until the bit is set again.

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INTERFACING WITH EXTERNAL MEMORY

Sometimes it is important to prevent another device from taking control of the bus while a block of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU from executing the protected block until current hold requests are serviced and the hold feature is disabled. This is illustrated in the following code:

	DI		;Disable interrupts to prevent
			;code interruption
	PUSH	WSR	;Disable hold requests and
	LDB	WSR,#1FH	;window Port 2
WAIT:	JBC	P2_PIN,6, WAIT	;Check the HLDA# signal. If set,
			;add protected instruction here
	POP	WSR	;Enable hold requests
	EI		;Enable interrupts
15.7.3	Hold Latency

When an external device asserts HOLD#, the microcontroller finishes the current bus cycle and then asserts HLDA#. The time it takes the microcontroller to assert HLDA# after the external device asserts HOLD# is called hold latency (see Figure 15-15). Table 15-9 lists the maximum hold latency for each type of bus cycle.

Table 15-9. Maximum Hold Latency

	Bus Cycle Type	Maximum Hold Latency
		(state times)
	Internal execution or idle mode	1.5
	16-bit external execution	2.5 + 1 per wait state
	8-bit external execution	2.5 + 2 per wait state

15.7.4 Regaining Bus Control

While HOLD# is asserted, the microcontroller continues executing code until it needs to access the external bus. If executing from internal memory, it continues until it needs to perform an external memory cycle. If executing from external memory, it continues executing until the queue is empty or until it needs to perform an external data cycle. As soon as it needs to access the external bus, the microcontroller asserts BREQ# and waits for the external device to deassert HOLD#. After asserting BREQ#, the microcontroller cannot respond to any interrupt requests, including NMI, until the external device deasserts HOLD#. One state time after HOLD# goes high, the microcontroller deasserts HLDA# and, with no delay, resumes control of the bus.

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