8XC196EA USER’S MANUAL

Table 6-8. Single Transfer Mode PTSCB

Unused

Unused

PTSDST (H) = 60H

PTSDST (L) = 00H

PTSSRC (H) = 00H

PTSSRC (L) = 20H

PTSCON = A5H (Mode = 101, BW = 0, SI/SU = 0, DI/DU = 1)

PTSCOUNT = 09H

6.6.4Block Transfer Mode

In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one memory location to another. See AP-445, 8XC196KR Peripherals: A User’s Point of View , for application examples with code. Figure 6-25 shows the PTS control block for block transfer mode.

In this mode, each PTS cycle consists of the transfer of an entire block of bytes or words. Because a PTS cycle cannot be interrupted, the block transfer mode can create long interrupt latency. The worst-case latency could be as high as 500 states if you assume a block transfer of 32 words from one external memory location to another, using an 8-bit bus with no wait states. See Table 6-6 on page 6-18 for execution times of PTS cycles.

The PTSCB in Table 6-9 sets up three PTS cycles that will transfer five bytes from memory locations 20–24H to 6000–6004H (cycle 1), 6005–6009H (cycle 2), and 600A–600EH (cycle 3). The source and destination are incremented after each byte transfer, but the original source address is reloaded into PTSSRC at the end of each block-transfer cycle. In this routine, the PTS always gets the first byte from location 20H.

Table 6-9. Block Transfer Mode PTSCB

Unused

PTSBLOCK = 05H

PTSDST (H) = 60H

PTSDST (L) = 00H

PTSSRC (H) = 00H

PTSSRC (L) = 20H

PTSCON = 37H (Mode = 001; DI, SI, DU, BW = 1; SU = 0)

PTSCOUNT = 03H

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STANDARD AND PTS INTERRUPTS

PTS Block Transfer Mode Control Block

In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).

7

0

Unused

0

0

0

0

0

0

0

0

7

0

PTSBLOCK

PTS Block Size

15

8

PTSDST (H)

PTS Destination Address (high byte)

7

0

PTSDST (L)

PTS Destination Address (low byte)

15

8

PTSSRC (H)

PTS Source Address (high byte)

7

0

PTSSRC (L)

PTS Source Address (low byte)

7

0

PTSCON

M2

M1

M0

BW

SU

DU

SI

DI

7

0

PTSCOUNT

Consecutive Block Transfers

Register

Location

Function

PTSBLOCK

PTSCB + 6

PTS Block Size

Specifies the number of bytes or words in each block. Valid values are

1–32, inclusive.

PTSDST

PTSCB + 4

PTS Destination Address

Write the destination memory location to this register. A valid address is

any unreserved memory location within page 00H; however, it must

point to an even address if word transfers are selected.

PTSSRC

PTSCB + 2

PTS Source Address

Write the source memory location to this register. A valid address is any

unreserved memory location within page 00H; however, it must point to

an even address if word transfers are selected.

Figure 6-25. PTS Control Block — Block Transfer Mode

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8XC196EA USER’S MANUAL

PTS Block Transfer Mode Control Block (Continued)

	Register	Location						Function
	PTSCON	PTSCB + 1	PTS Control Bits
			M2:0	PTS Mode
				These bits select the PTS mode:
				M2		M1	M0
				0		0	1	block transfer mode
			BW	Byte/Word Transfer
				0	= word transfer
				1	= byte transfer
			SU	Update PTSSRC
				0	=	reload original PTS source address after each block
						transfer is complete
				1	=	retain current PTS source address after each block transfer
						is complete
			DU	Update PTSDST
				0	=	reload original PTS destination address after each block
						transfer is complete
				1	=	retain current PTS destination address after each block
						transfer is complete
			SI	PTSSRC Autoincrement
				0	=	the contents of PTSSRC are not incremented after each
						byte or word transfer
				1	=	the contents of PTSSRC are incremented after each byte
						or word transfer
			DI	PTSDST Autoincrement
				0	=	the contents of PTSDST are not incremented after each
						byte or word transfer
				1	=	the contents of PTSDST are incremented after each byte or
						word transfer
	PTSCOUNT	PTSCB + 0	Consecutive Block Transfers
			Defines the number of blocks that will be transferred during the block
			transfer routine. Each block transfer is one PTS cycle. Maximum number
			is 255.

Figure 6-25. PTS Control Block — Block Transfer Mode (Continued)

6.6.5Dummy Mode

The PTS dummy mode protects against situations where software manually clears the pending bits in the PIHx_PEND register before clearing the PIHx_PTS interrupt pending bit in the INT_PEND1 register. In this situation, the CPU may attempt to service the interrupt request after it is no longer valid. If this occurs, the PIH responds with the dummy PTS request vector address (2016H). The PTS aborts service when it reads the PTSCB and determines that the PTS dummy mode is selected. Write 0000H to location FF2016H so that the dummy PTS routine vectors to the zero-register and no register RAM locations are wasted. Figure 6-26 shows the PTS control block for dummy mode.

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STANDARD AND PTS INTERRUPTS

PTS Dummy Mode Control Block

In dummy mode, the PTS control block contains only a control register (PTSCON). All other PTSCB bytes can be used as extra RAM.

	7												0
PTSCON		M2	M1	M0			0		0		0	0	0
		7											0
Unused
		0	0	0			0		0		0	0	0
Register	Location								Function
Register	Location								Function
PTSCON	PTSCB + 1		PTS Control Bits
			M2:0	PTS Mode
				These bits select the PTS mode:
				M2	M1		M0
				0	0		0	dummy mode

Figure 6-26. PTS Control Block — Dummy Mode

6.6.6Missed-Event Mode

In missed-event mode, the PTS uses a pair of event processor array (EPA) capture/compare channels to generate an interrupt if an input pulse fails to occur within a predictable period of time (Figure 6-27). The PTS monitors a series of regular input pulses on the EPA channel and calculates when the next pulse should occur based upon the time of the last two pulses. It stores the calculated value into the event-time register (EPAx_TIME) of a second EPA channel. The second EPA channel compares the timer value to the contents of EPAx_TIME. If the next pulse does not occur before the two values are equal, an interrupt occurs. Figure 6-28 shows the PTS control block for missed-event mode.

Missing Pulse(s)

A4295-01

Figure 6-27. An Example of a Missed Event

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8XC196EA USER’S MANUAL

PTS Missed-event Mode Control Block

In missed-event mode, the PTS control block contains a pointer to the current event-time (PTSCUR), a pointer to the previous event-time (PTSPREV), a control register (PTSCON), and a maximum count register (PTSCOUNT).

		7											0
Unused			0	0	0	0			0	0		0	0
			7										0
Unused
			0	0	0	0			0	0		0	0
			15										8
PTSPREV (H)					Pointer to Previous Event Time (high byte)
			7										0
PTSPREV (L)
					Pointer to Previous Event Time (low byte)
			15										8
PTSCUR (H)					Pointer to Current Event Time (high byte)
			7										0
PTSCUR (L)					Pointer to Current Event Time (low byte)
			7										0
PTSCON
			M2	M1	M0	BW			0	0		0	0
			7										0
PTSCOUNT						Maximum Count
Register		Location							Function
PTSPREV		PTSCB + 4		Pointer to Previous Event Time
				This register points to the memory location where the PTS stores the
				time of the previous event. A valid address is any unreserved memory
				location within page 00H; however, it must point to an even address if
				word event times are selected.
PTSCUR		PTSCB + 2		Pointer to Current Event Time
				This register points to the event-time register (EPAx_TIME) for the EPA
				channel that is capturing the input pulse signal.

Figure 6-28. PTS Control Block — Missed-event Mode

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STANDARD AND PTS INTERRUPTS

PTS Missed-event Mode Control Block (Continued)

Register	Location					Function
PTSCON	PTSCB + 1 PTS Control Bits
		M2:0	PTS Mode
			These bits select the PTS mode:
			M2	M1	M0
			1	1	0	missed-event mode
		BW	Byte/Word Event-time Value

0 = word

1 = byte

4:0 To guarantee proper device operation, write zeros to these bits.

PTSCOUNT PTSCB + 0 Maximum Count

Defines the number of times the PTS will check for the occurrence of an event. Each comparison is one PTS cycle. Maximum number is 255.

Figure 6-28. PTS Control Block — Missed-event Mode (Continued)

To use the missed-event mode, configure one event processor array (EPA) channel to capture events and a second EPA channel to monitor a timer/counter and compare its value with the expected next event time. For example, configure EPA1 as the input capture channel and EPA0 as the compare-only channel.

Configure EPA1 to select timer 1, capture on rising edge, select associated pin for input, reset timer 1, old data lost on overrun, no module concantenation (EPA1_CON = 0000 0010 X0X0 0010).

Configure EPA0 to select timer 1, compare mode, interrupt only, no action (EPA0_CON = 0000 0100 0000 0000).

Initialize the PTSCB as shown in Table 6-10.

Table 6-10. Missed-event Mode PTSCBs

0000H (Unused)

0000H (Unused)

PTSPREV (H) = xxH (any unreserved memory location within page 00H)

PTSPREV (L) = xxH (any unreserved memory location within page 00H)

PTSCUR (H) = 1FH (EPA1_TIME)

PTSCUR (L) = 5AH (EPA1_TIME)

PTSCON = C0H (missed-event mode)

PTSCOUNT = FFH (check for 255 events)

Whenever an event occurs on EPA1, the EPA loads the value of the reference timer into the EPA1_TIME register. The PTS uses two temporary registers to calculate the expected next event time. The following steps outline a missed-event PTS cycle.

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8XC196EA USER’S MANUAL

1.EPA1 captures an event and the value of the reference timer is loaded into EPA1_TIME.

2.The PTS subtracts the time of the previous event, which is stored in a memory location pointed to by the PTSPREV register, from the current event-time stored in EPA1_TIME. It then loads the result into a temporary register.

TEMP1 ← (EPA1_TIME) – (PTSPREV)

For example, assume that the previous event occurred at timer value 04H and the current event occurred at timer value 08H. The PTS would load 04H into TEMP1.

3.To calculate the expected next event time, the PTS divides the contents of the temporary register (TEMP1) by two and loads the result into a second temporary register (TEMP2). It then adds the contents of TEMP1 to the contents of TEMP2 and loads the result into TEMP1. Then the PTS adds TEMP1 to the current event-time value to calculate the next event time. It stores this value in TEMP1.

TEMP2 ← TEMP1/2 TEMP1 ← TEMP1 + TEMP2

TEMP1 ← TEMP1 + EPA1_TIME

In the case of our example, TEMP1 would now contain 0EH.

4.The PTS loads the expected next event time into the location pointed to by EPA1_TIME + 4, which in this example, is the address of the EPA0_TIME register.

(EPA0_TIME) ← TEMP1

5.The PTS then loads the current event-time value into the location pointed to by the PTSPREV register.

(PTSPREV) ← (EPA1_TIME)

6.Finally, the PTS decrements the PTSCOUNT register.

PTSCOUNT ← PTSCOUNT – 1

If a match occurs between the reference timer and the contents of EPA0_TIME, EPA0 causes an interrupt which indicates a missed-event. As long as an event occurs on EPA1 before a match occurs between the reference timer and the contents of EPA0_TIME, the PTS cycle repeats until PTSCOUNT decrements to zero. When PTSCOUNT reaches zero, the PTS generates an end-of- PTS interrupt.

6-44

7

I/O Ports