I/O PORTS

7.3USING THE SPECIAL-FUNCTION SIGNALS

Most port pins can function as either general-purpose I/O signals or as special-function signals. The following sections describe the special-function signals and outline special considerations for using these signals.

7.3.1Address and Data Signals (Ports 3, 4, and EPORT)

During external memory bus cycles, the processor takes control of ports 3 and 4 and automatically configures them as complementary output ports for driving the lower 16 address signals and/or the data bus or as inputs for reading the data bus. When EA# is inactive, these port pins are available for general-purpose I/O when the microcontroller is not performing external bus cycles.

Some of the extended port pins can function as address signals or general-purpose I/O signals (Table 7-7). To use an extended port pin as an address signal, set the corresponding EP_MODE bit, selecting special-function mode. When an extended port pin is configured as an address signal, the microcontroller automatically configures the pin as a complementary output.

When EA# is inactive, ports 3 and 4 output the contents of the P3_REG and P4_REG registers. Because these registers reset to FFH and the P34_DRV register resets to 00H (open-drain mode), ports 3 and 4 will float unless you connect external pull-up resistors to the pins, write zeros to the P3_REG and P4_REG registers, or write ones to the P34_DRV register.

Table 7-7. Address and Data Signals

Address Signal	I/O Signal	Address Signal Description and Considerations
AD15:8	P4.7:0	Description:
AD7:0	P3.7:0	Address/Data Lines. The function of these pins depend on the
		bus size and mode. When a bus access is not occurring, these
		pins revert to their I/O port function.
		16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0–15
		during the first half of the bus cycle and drive or receive data
		during the second half of the bus cycle.
		8-bit Multiplexed Bus Mode: AD15:8 drive address bits 8–15
		during the entire bus cycle. AD7:0 drive address bits 0–7 during
		the first half of the bus cycle and drive or receive data during the
		second half of the bus cycle.
		16-bit Demultiplexed Mode: AD15:0 drive or receive data during
		the entire bus cycle.
		8-bit Demultiplexed Mode: AD7:0 drive or receive data during the
		entire bus cycle. AD15:8 drive the data that is currently on the
		high byte of the internal bus.

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Table 7-7. Address and Data Signals (Continued)

Address Signal	I/O Signal	Address Signal Description and Considerations
A20:16	EPORT.4:0	Description:
		Address Lines 16–20. These address lines provide address bits
		16–20 during the entire external memory cycle, supporting
		extended addressing of the 2-Mbyte address space.
		Considerations:
		During the CCB fetch, all EPORT pins are strongly driven high.
		Designers should ensure that this does not conflict with external
		systems that are outputting signals to the EPORT.
		When EPORT pins are floated during idle, powerdown, or hold,
		the external system must provide circuitry to prevent CMOS
		inputs on external devices from floating. During powerdown, the
		EPORT input buffers on pins configured for their extended-
		address function are disconnected from the pins, so a floating pin
		will not cause increased power consumption.
		Open-drain outputs require an external pull-up resistor. Inputs
		must be driven or pulled high or low; they must not be allowed to
		float.

7.3.1.1EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold

During reset, the EPORT pins are forced to their extended-address functions and are weakly pulled high. During the CCB fetch, FFH is strongly driven onto the pins. This value remains strongly driven until either the pin is configured for I/O or a different extended address is accessed. If the pins remain configured as extended-address functions, they are placed in a high-imped- ance state during idle, powerdown, and hold. If they are configured as I/O, they retain their I/O function during those modes. See Figure 13-7 on page 13-9 and Table B-5 on page B-15 for additional information.

7.3.2Bus-control Signals (Ports 2 and 5)

Some port 2 and 5 pins function as either general-purpose I/O signals or as bus-control signals (Table 7-8). To use a port 2 pin as a bus-control signal, set the corresponding P2_MODE bit, selecting special-function mode. To configure a port 2 pin as a complementary output signal, clear the corresponding P2_DIR bit. To configure a port 2 pin as an input signal, set the corresponding P2_DIR and P2_REG bits. To configure a port 2 pin as an open-drain output, set the corresponding P2_DIR bit. To use a port 5 pin as a bus-control signal, set the corresponding P5_MODE bit; this selects special-function mode. For port 5, when a pin is configured as a bus-control signal, the microcontroller automatically configures the pin as a complementary output or high-imped- ance input signal, depending on the bus-control signal function.

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I/O PORTS

			Table 7-8. Bus-control Signals
	Bus-control	I/O	Bus-control Signal Description and Considerations
	Signal	Signal
	ALE	P5.0	Description:
			Address Latch Enable. This active-high output signal is asserted only during
			external memory cycles. ALE signals the start of an external bus cycle and
			indicates that valid address information is available on the system address/data
			bus.
			Considerations:
			When the boot code is located in external memory (EA# active), the microcon-
			troller automatically configures P5.0 at reset as a special-function complementary
			output signal.
			When the boot code is located in internal memory (EA# inactive), P5.0 is weakly
			held high. Set P5_MODE.0 to turn off the internal pull-up and configure P5.0 as a
			special-function complementary output signal.
	BHE#	P5.5	Description:
			Byte High Enable. During 16-bit bus cycles, this active-low output signal is
			asserted for word and high-byte reads and writes to external memory. BHE#
			indicates that valid data is being transferred over the upper half of the system data
			bus.
			Considerations:
			If EA# is high on reset (internal access), P5.5 is weakly held high until your
			software writes to P5_MODE.5. If EA# is low on reset (external access), P5.5 is
			weakly held high until the CCB0 fetch is completed. If CCR0.2 is clear, the micro-
			controller automatically configures this pin as WRH#. If CCR0.2 is set, the micro-
			controller automatically configures this pin as BHE#.
	BREQ#	P5.4	Description:
			Bus Request. This active-low output signal is asserted during a hold cycle when
			the bus controller has a pending external memory cycle.
			Considerations:
			When the bus-hold protocol is enabled (WSR.7 is set), the P5.4/BREQ# pin can
			function only as BREQ#, regardless of the configuration selected through the port
			configuration registers (P5_MODE, P5_DIR, and P5_REG). An attempt to change
			the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
			cleared).
			The microcontroller can assert BREQ# at the same time as or after it asserts
			HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
	CLKOUT	P2.7	Description:
			Clock Output. Output of the internal clock generator. The CLKOUT frequency can
			be programmed to one of five frequencies: the internal operating frequency (f)
			divided by a factor of two, four, eight, or sixteen, or the same frequency as the
			oscillator input (FXTAL1).
			Considerations:
			Following reset, the microcontroller automatically configures P2.7 as CLKOUT. It is
			not held high. When P2.7 is configured as CLKOUT (P2_MODE.7 = 1), it is always
			a complementary output.

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			Table 7-8. Bus-control Signals (Continued)
	Bus-control	I/O	Bus-control Signal Description and Considerations
	Signal	Signal
	HLDA#	P2.6	Description:
			Bus Hold Acknowledge. The HLDA# pin is used in systems with more than one
			processor using the system bus. The microcontroller asserts HLDA# to indicate
			that it has released the bus in response to HOLD# and another processor can take
			control. (This signal is active low to avoid misinterpretation by external hardware
			immediately after reset.)
			Considerations:
			When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can
			function only as HLDA#, regardless of the configuration selected through the port
			configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change
			the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
			cleared).
	HOLD#	P2.5	Description:
			Bus Hold Request. An external device uses this active-low input signal to request
			control of the bus.
			Considerations:
			When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can
			function only as HOLD#, regardless of the configuration selected through the port
			configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change
			the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
			cleared). If P2.5 is configured as a general-purpose I/O signal, the device does not
			recognize signals on this pin as HOLD#. Instead, the bus controller receives an
			internal HOLD signal. This enables the device to access the external bus while it is
			performing I/O at P2.5.
	INST	P5.1	Description:
			Instruction Fetch. When high, INST indicates that an instruction is being fetched
			from external memory. The signal remains high during the entire bus cycle of an
			external instruction fetch. INST is low for data accesses, including interrupt vector
			fetches and chip configuration byte reads. INST is low during internal memory
			fetches.
			Considerations:
			Following reset, pin P5.1 is weakly held high until your software writes configu-
			ration data into P5_MODE.
	READY	P5.6	Description:
			Ready Input. This active-high input can be used to insert wait states in addition to
			those programmed in the chip configuration byte 0 (CCB0) and the bus control x
			register (BUSCONx). CCB0 is programmed with the minimum number of wait
			states (0–3) for an external fetch of CCB1 and BUSCONx is programmed with the
			minimum number of wait states (0–3) for all external accesses to the address
			range assigned to the chip-select x channel. If READY is low when the
			programmed number of wait states is reached, additional wait states are added
			until READY is pulled high.
			Considerations:
			Following reset, pin P5.6 is weakly held high until your software writes configu-
			ration data into P5_MODE.

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I/O PORTS

			Table 7-8. Bus-control Signals (Continued)
	Bus-control	I/O	Bus-control Signal Description and Considerations
	Signal	Signal
	RD#	P5.3	Description:
			Read. Read-signal output to external memory. RD# is asserted only during
			external memory reads.
			Considerations:
			If EA# is high on reset (internal access), P5.3 is weakly held high until your
			software writes to P5_MODE. If EA# is low on reset (external access), the micro-
			controller automatically configures P5.3 as a special-function complementary
			output signal.
	WR#	P5.2	Description:
			Write. This active-low output indicates that an external write is occurring. This
			signal is asserted only during external memory writes.
			Considerations:
			The chip configuration register 0 (CCR0) determines whether this pin functions as
			WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
			Following reset, pin P5.2 is weakly held high until your software writes configu-
			ration data into P5_MODE.
	WRL#	P5.2	Description:
			Write Low. During 16-bit bus cycles, this active-low output signal is asserted for
			low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL#
			is asserted for all write operations.
			Considerations:
			The chip configuration register 0 (CCR0) determines whether this pin functions as
			WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
			Following reset, pin P5.2 is weakly held high until your software writes configu-
			ration data into P5_MODE.
	WRH#	P5.5	Description:
			Write High. During 16-bit bus cycles, this active-low output signal is asserted for
			high-byte writes and word writes to external memory. During 8-bit bus cycles,
			WRH# is asserted for all write operations.
			Considerations:
			If EA# is high on reset (internal access), P5.5 is weakly held high until your
			software writes to P5_MODE.5. If EA# is low on reset (external access), P5.5 is
			weakly held high until the CCB0 fetch is completed. If CCR0.2 is clear, the micro-
			controller automatically configures this pin as WRH#. If CCR0.2 is set, the micro-
			controller automatically configures this pin as BHE#.

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8XC196EA USER’S MANUAL

7.3.3Chip-select Signals (EPORT)

Some EPORT pins function as chip-select signals or general-purpose I/O (Table 7-9). To use an EPORT pin as a chip-select signal, set the corresponding EP_MODE bit, selecting special-func- tion mode, and clear the corresponding EP_DIR bit, selecting a complementary output configuration.

Table 7-9. Chip-select Signals

Chip-select Signal	I/O Signal	Chip-select Signal Descriptions and Considerations
CS2:0#	EPORT.7:5	Description:
		Chip-select Lines 0–2. The active-low output CSx# is asserted
		during an external memory cycle when the address to be
		accessed is in the range programmed for chip select x.
		Considerations:
		Pins EPORT.7:5 are weakly pulled high during reset. After reset,
		EPORT.5 defaults to the CS0# function. This chip-select signal
		detects address ranges that contain the CCBs and FF2080H
		(program start-up address).
		The bus configuration programmed in BUSCONx applies to
		address range x, regardless of the port configuration.

7.3.4EPA and Timer Signals (Ports 7–10)

The ports 7–10 pins can function as EPA and timer signals or general-purpose I/O signals (). To use the ports 7–10 pins as EPA and timer signals, set the corresponding P x_MODE bits, selecting special-function mode. To configure an EPA or timer signal as a complementary output, clear the corresponding Px_DIR bit. To configure an EPA or timer signal as an input, set the corresponding Px_DIR and Px_REG bits. To configure an EPA or timer signal as an open-drain output, set the corresponding Px_DIR bit.

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			Table 7-10. EPA and Timer Signals
	EPA or Timer	I/O	EPA, Enhanced EPA, or Timer Signal
	Signal	Signal	Descriptions and Considerations
	EPA16	P10.4	Description:
	EPA15:8	P8.7:0	Event Processor Array (EPA) Capture/Compare Channels. High-speed
	EPA7:0	P7.7:0
			input/output signals for the EPA capture/compare channels.
			Considerations:
			Following reset, these pins are weakly pulled high until your software
			writes configuration data into Px_MODE.
	OS7:0	P9.7:0	Description:
			Event Processor Array (EPA) Compare-only Channels with Simulcapture.
			Outputs of the EPA’s compare-only channels. These pins are multiplexed
			with port 9 and may be configured as standard I/O.
			Considerations:
			Following reset, pins P9.7:0 are weakly pulled high until your software
			writes configuration data into P9_MODE.
	T1CLK	P7.0	Description:
	T2CLK	P7.2	Timer x External Clock. External clock for timer x. Timer x is program-
	T3CLK	P7.4
			mable to increment or decrement on the rising edge, the falling edge, or
	T4CLK	P7.6
			both rising and falling edges of TxCLK.
			Considerations:
			Following reset, pins P7.0, P7.2, P7.4, and P7.6 are weakly pulled high
			until your software writes configuration data into P7_MODE.
	T1RST	P7.1	Description:
	T2RST	P7.3	Timer x External Reset. External reset for timer x. Timer x is program-
	T3RST	P7.5
			mable to reset on the rising edge, the falling edge, or both rising and
	T4RST	P7.6
			falling edges of TxRST.
			Considerations:
			Following reset, pins P7.1, P7.3, P7.5, and P7.6 are weakly pulled high
			until your software writes configuration data into P7_MODE.

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