8XC196EA USER’S MANUAL

FIGURES

Figure		Page
2-1	83C196EA Detailed Block Diagram .............................................................................	2-3
2-2	80C196EA Detailed Block Diagram .............................................................................	2-4
2-3	83C196EA Simplified Block Diagram ..........................................................................	2-5
2-4	Block Diagram of the Core ..........................................................................................	2-6
2-5	Clock Circuitry ..............................................................................................................	2-9
2-6	Internal Clock Phases (Assuming PLL is Bypassed)..................................................	2-10
2-7	Effect of Clock Mode on Internal CLKOUT Frequency...............................................	2-11
2-8	CLKOUT Control (CLKOUT_CON) Register ..............................................................	2-12
2-9	Chip Configuration 0 (CCR0) Register .......................................................................	2-17
2-10	Chip Configuration 1 (CCR1) Register .......................................................................	2-20
4-1	16-Mbyte Address Space ............................................................................................	4-2
4-2	Pages FFH and 00H ..................................................................................................	4-3
4-3	Internal RAM Control (IRAM_CON) Register .............................................................	4-10
4-4	Register File Memory Map .........................................................................................	4-15
4-5	Windowing ..................................................................................................................	4-18
4-6	Window Selection (WSR) Register.............................................................................	4-19
4-7	Window Selection 1 (WSR1) Register........................................................................	4-19
4-8	Chip Configuration 0 (CCR0) Register .......................................................................	4-27
4-9	Chip Configuration 1 (CCR1) Register .......................................................................	4-30
5-1	Stack Overflow Module Block Diagram ........................................................................	5-1
5-2	Stack Pointer (SP) ........................................................................................................	5-3
5-3	Lower Stack Limit (STACK_BOTTOM) Register ..........................................................	5-4
5-4	Upper Stack Limit (STACK_TOP) Register ..................................................................	5-4
6-1	Interrupt Structure Block Diagram ................................................................................	6-2
6-2	Interrupt Service Flow Diagram ...................................................................................	6-3
6-3	Peripheral Interrupt Handler x Vector Index (PIHx_VEC_IDX) Registers ....................	6-8
6-4	Peripheral Interrupt Handler x Vector Base (PIHx_VEC_BASE) Registers ...............	6-13
6-5	Peripheral Interrupt Handler (PIH) Interrupt Sources .................................................	6-15
6-6	Worst-case Interrupt Response Time.........................................................................	6-17
6-7	PTS Interrupt Response Time ....................................................................................	6-18
6-8	Interrupt Mask (INT_MASK) Register.........................................................................	6-20
6-9	Interrupt Mask 1 (INT_MASK1) Register....................................................................	6-21
6-10	PIH0 Interrupt Mask (PIH0_INT_MASK) Register......................................................	6-21
6-11	PIH1 Interrupt Mask (PIH1_INT_MASK) Register......................................................	6-22
6-12	PTS Select (PTSSEL) Register ..................................................................................	6-23
6-13	PIH0 PTS Select (PIH0_PTSSEL) Register ...............................................................	6-24
6-14	PIH1 PTS Select (PIH1_PTSSEL) Register ...............................................................	6-25
6-15	Interrupt Pending (INT_PEND) Register ....................................................................	6-28
6-16	Interrupt Pending 1 (INT_PEND1) Register ...............................................................	6-29
6-17	PIH0 Interrupt Pending (PIH0_INT_PEND) Register .................................................	6-29
6-18	PIH1 Interrupt Pending (PIH1_INT_PEND) Register .................................................	6-30
6-19	PTS Control Blocks ....................................................................................................	6-31
6-20	PTS Service (PTSSRV) Register ...............................................................................	6-32
6-21	PIH0 PTS Service (PIH0_PTSSRV) Register ............................................................	6-33

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		CONTENTS
	FIGURES
Figure		Page
6-22	PIH1 PTS Service (PIH1_PTSSRV) Register ............................................................	6-34
6-23	PTS Mode Selection Bits (PTSCON Bits 7:5) ............................................................	6-35
6-24	PTS Control Block — Single Transfer Mode ..............................................................	6-36
6-25	PTS Control Block — Block Transfer Mode ...............................................................	6-39
6-27	An Example of a Missed Event ..................................................................................	6-41
6-26	PTS Control Block — Dummy Mode ..........................................................................	6-41
6-28	PTS Control Block — Missed-event Mode .................................................................	6-42
7-1	EPORT Pins 0–4 Internal Structure............................................................................	7-23
7-2	Ports 2, 5, 7–12, and EPORT Pins 5–7 Internal Structure .........................................	7-25
7-3	Ports 3 and 4 Internal Structure .................................................................................	7-27
8-1	SIO Block Diagram (Mode 0)........................................................................................	8-2
8-2	SIO Block Diagram (Modes 1, 2, and 3).......................................................................	8-3
8-3	Mode 0 Timing..............................................................................................................	8-6
8-4	Serial Port Frames for Mode 1 .....................................................................................	8-8
8-5	Serial Port Frames in Mode 2 and 3.............................................................................	8-9
8-6	Serial Port Control (SPx_CON) Register....................................................................	8-12
8-7	Serial Port x Baud Rate (SPx_BAUD) Register..........................................................	8-14
8-8	Serial Port Status (SPx_STATUS) Register...............................................................	8-17
9-1	Standard Mode Configuration Options .........................................................................	9-2
9-2	Duplex Mode Configuration Options.............................................................................	9-3
9-3	Channel-select Configuration Options..........................................................................	9-4
9-4	Serial Clock Options for Transmissions........................................................................	9-9
9-5	Serial Clock Options for Receptions...........................................................................	9-10
9-6	Relationship Between Clock and Data Signals (Handshaking Transfers)..................	9-11
9-7	Synchronous Serial Port Baud (SSIO_BAUD) Register .............................................	9-13
9-8	Synchronous Serial Control x (SSIOx_CON) Registers .............................................	9-15
9-9	SSIO 0 Clock (SSIO0_CLK) Register.........................................................................	9-17
9-10	SSIO 1 Clock (SSIO1_CLK) Register.........................................................................	9-18
9-11	Synchronous Serial x Buffer (SSIOx_BUF) Register..................................................	9-20
9-12	Variable-width MSB in SSIO Transmissions ..............................................................	9-21
10-1	PWM Block Diagram ..................................................................................................	10-2
10-2	PWM Output Waveforms............................................................................................	10-5
10-3	PWM Period (PWMx_y_PERIOD) Register ...............................................................	10-7
10-4	PWM Control (PWMx_CONTROL, PWMy_CONTROL) Registers ............................	10-8
10-5	PWM Count (PWMx_y_COUNT) Register .................................................................	10-9
10-6	D/A Buffer Block Diagram.........................................................................................	10-10
10-7	PWM to Analog Conversion Circuitry .......................................................................	10-10
11-1	EPA Block Diagram ....................................................................................................	11-2
11-2	EPA Timer/Counters ..................................................................................................	11-7
11-3	Sharing the Time Bus .................................................................................................	11-8
11-4	A Single EPA Capture/Compare Channel................................................................	11-10
11-5	EPA Simplified Input Capture Structure ...................................................................	11-11
11-6	Valid EPA Input Events ............................................................................................	11-11
11-7	Generating a 32-bit Time Value ...............................................................................	11-13

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8XC196EA USER’S MANUAL

FIGURES

Figure		Page
11-8	Timer 1 Overflow Occurrence ..................................................................................	11-13
11-9	Controlling a Pair of Adjacent Pins ...........................................................................	11-14
11-10	Generating Two Edges on One Pin..........................................................................	11-14
11-11	Timer x Control (TxCONTROL) Register..................................................................	11-15
11-12	Timer/Counter Multiplexer (TIMER_MUX) Register .................................................	11-18
11-13	Timer x Time (TIMERx) Registers ............................................................................	11-18
11-14	EPA Control (EPAx_CON) Registers .......................................................................	11-19
11-15	EPA Time (EPAx_TIME) Registers ..........................................................................	11-22
11-16	Output/Simulcapture x Control (OSx_CON) Register...............................................	11-23
11-17	Output Simulcapture x Time (OSx_TIME) Register..................................................	11-25
11-18	PIH0 Interrupt Mask (PIH0_INT_MASK) Register....................................................	11-26
11-19	PIH1 Interrupt Mask (PIH1_INT_MASK) Register....................................................	11-26
11-20	Interrupt Mask (INT_MASK) Register.......................................................................	11-27
11-21	Interrupt Mask 1 (INT_MASK1) Register..................................................................	11-28
12-1	A/D Converter Block Diagram ....................................................................................	12-1
12-2	A/D Test (AD_TEST) Register....................................................................................	12-5
12-3	A/D Result (AD_RESULT) Register — Write Format .................................................	12-7
12-4	A/D Time (AD_TIME) Register ...................................................................................	12-8
12-5	A/D Command (AD_COMMAND) Register ................................................................	12-9
12-6	A/D Scan (AD_SCAN) Register................................................................................	12-10
12-7	A/D Result (AD_RESULT) Register — Read Format...............................................	12-12
12-8	A/D Result x (AD_RESULTx) Register — Read Format ..........................................	12-13
12-9	Idealized A/D Sampling Circuitry ..............................................................................	12-14
12-10	Suggested A/D Input Circuit .....................................................................................	12-16
12-11	Ideal A/D Conversion Characteristic.........................................................................	12-19
12-12	Actual and Ideal A/D Conversion Characteristics.....................................................	12-20
12-13	Terminal-based A/D Conversion Characteristic .......................................................	12-22
13-1	Minimum Hardware Connections ...............................................................................	13-3
13-2	Power and Return Connections .................................................................................	13-4
13-3	On-chip Oscillator Circuit............................................................................................	13-6
13-4	External Crystal Connections .....................................................................................	13-7
13-5	External Clock Connections .......................................................................................	13-8
13-6	External Clock Drive Waveforms................................................................................	13-8
13-7	Reset Timing Sequence .............................................................................................	13-9
13-8	Internal Reset Circuitry .............................................................................................	13-10
13-9	Minimum Reset Circuit .............................................................................................	13-11
13-10	Example of a System Reset Circuit ..........................................................................	13-11
13-11	Reset Source (RSTSRC) Register ...........................................................................	13-13
14-1	Clock Control During Power-saving Modes................................................................	14-4
14-2	Power-up and Power-down Sequence When Using an External Interrupt.................	14-8
14-3	External RC Circuit .....................................................................................................	14-8
14-4	Typical Voltage on the RPD Pin While Exiting Powerdown......................................	14-10
15-1	Calculation of a Chip-select Output ............................................................................	15-9
15-2	Address Compare (ADDRCOMx) Registers.............................................................	15-10

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	FIGURES
Figure		Page
15-3	Address Mask (ADDRMSKx) Registers ...................................................................	15-11
15-4	Bus Control (BUSCONx) Registers ..........................................................................	15-13
15-5	Example System for Setting Up Chip-select Outputs ...............................................	15-15
15-6	Chip Configuration 0 (CCR0) Register .....................................................................	15-17
15-7	Chip Configuration 1 (CCR1) Register .....................................................................	15-19
15-8	Multiplexing and Bus Width Options.........................................................................	15-22
15-9	Bus Activity for Four Types of Buses........................................................................	15-23
15-10	16-bit External Devices in Demultiplexed Mode .......................................................	15-25
15-11	Timings for Multiplexed and Demultiplexed 16-bit Buses.........................................	15-26
15-12	Timings for Multiplexed and Demultiplexed 8-bit Buses...........................................	15-28
15-13	READY Timing Diagram — Multiplexed Mode .........................................................	15-30
15-14	READY Timing Diagram — Demultiplexed Mode ....................................................	15-31
15-15	HOLD#, HLDA# Timing ............................................................................................	15-33
15-16	Write-control Signal Waveforms ...............................................................................	15-36
15-17	Decoding WRL# and WRH#.....................................................................................	15-38
15-18	A System with 8-bit and 16-bit Buses.......................................................................	15-39
15-19	Multiplexed System Bus Timing ...............................................................................	15-40
15-20	Demultiplexed System Bus Timing...........................................................................	15-41
15-21	Deferred Bus-cycle Mode Timing Diagram...............................................................	15-42
16-1	SDU Block Diagram....................................................................................................	16-1
16-2	SDU Functional Block Diagram ..................................................................................	16-3
16-3	SDU State Machine Diagram .....................................................................................	16-4
16-4	Code RAM Access State Machine Diagram...............................................................	16-5
16-5	SDU Master/Slave Configuration................................................................................	16-7
16-6	SDU Transmit/Receive Timings .................................................................................	16-7
16-7	Serial Debug Unit Command Byte (SDU_COM) Register..........................................	16-8
16-8	Breakpoint Logic Block Diagram ..............................................................................	16-11
16-9	Code RAM Word Read Sequence............................................................................	16-12
16-10	Code RAM Byte Write Sequence .............................................................................	16-13
16-11	SDU Interface Connector .........................................................................................	16-14
17-1	Chip Configuration 0 (CCR0) Register .......................................................................	17-3
17-2	ROM-dump Circuit......................................................................................................	17-6
17-3	Serial Port Mode Circuit..............................................................................................	17-9
17-4	SDU RISM Control Block..........................................................................................	17-11
17-5	SDU RISM Execution Circuit ....................................................................................	17-14
B-1	83C196EA 160-pin QFP Package...............................................................................	B-3
B-2	80C196EA 160-pin QFP Package...............................................................................	B-4
C-1	A/D Command (AD_COMMAND) Register .................................................................	C-9
C-2	A/D Result (AD_RESULT) Register — Read Format................................................	C-10
C-3	A/D Result (AD_RESULT) Register — Write Format ................................................	C-11
C-4	A/D Result x (AD_RESULTx) Register — Read Format ...........................................	C-12
C-5	A/D Scan (AD_SCAN) Register.................................................................................	C-13
C-6	A/D Test (AD_TEST) Register...................................................................................	C-14
C-7	A/D Time (AD_TIME) Register ..................................................................................	C-15

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8XC196EA USER’S MANUAL

FIGURES

Figure		Page
C-8	Address Compare (ADDRCOMx) Registers..............................................................	C-16
C-9	Address Mask (ADDRMSKx) Registers ....................................................................	C-17
C-10	Bus Control (BUSCONx) Registers ...........................................................................	C-18
C-11	Chip Configuration 0 (CCR0) Register ......................................................................	C-19
C-12	Chip Configuration 1 (CCR1) Register ......................................................................	C-21
C-13	CLKOUT Control (CLKOUT_CON) Register .............................................................	C-23
C-14	Extended Port I/O Direction (EP_DIR) Register ........................................................	C-24
C-15	Extended Port Mode (EP_MODE) Register ..............................................................	C-25
C-16	Extended Port Input (EP_PIN) Register ....................................................................	C-26
C-17	Extended Port Data Output (EP_REG) Register .......................................................	C-27
C-18	EPA Control (EPAx_CON) Registers ........................................................................	C-28
C-19	EPA Time (EPAx_TIME) Registers ...........................................................................	C-32
C-20	Interrupt Mask (INT_MASK) Register........................................................................	C-33
C-21	Interrupt Mask 1 (INT_MASK1) Register...................................................................	C-34
C-22	Interrupt Pending (INT_PEND) Register ...................................................................	C-35
C-23	Interrupt Pending 1 (INT_PEND1) Register ..............................................................	C-36
C-24	Internal RAM Control (IRAM_CON) Register ............................................................	C-37
C-25	Ones Register (ONES_REG) ....................................................................................	C-38
C-26	Output/Simulcapture x Control (OSx_CON) Register................................................	C-39
C-27	Output Simulcapture x Time (OSx_TIME) Register...................................................	C-42
C-28	Port x I/O Direction (Px_DIR) Register .....................................................................	C-43
C-29	Port x Mode (Px_MODE) Register ............................................................................	C-44
C-30	Port x Pin Input (Px_PIN) Register............................................................................	C-46
C-31	Port x Data Output (Px_REG) Register.....................................................................	C-47
17-6	Port 3/4 Push-pull Enable (P34_DRV) Register ........................................................	C-49
17-7	PIH0 Interrupt Mask (PIH0_INT_MASK) Register.....................................................	C-50
17-8	PIH1 Interrupt Mask (PIH1_INT_MASK) Register.....................................................	C-51
17-9	PIH0 Interrupt Pending (PIH0_INT_PEND) Register ................................................	C-52
17-10	PIH1 Interrupt Pending (PIH1_INT_PEND) Register ................................................	C-53
17-11	PIH0 PTS Select (PIH0_PTSSEL) Register ..............................................................	C-54
17-12	PIH1 PTS Select (PIH1_PTSSEL) Register ..............................................................	C-55
17-13	PIH0 PTS Service (PIH0_PTSSRV) Register ...........................................................	C-56
17-14	PIH1 PTS Service (PIH1_PTSSRV) Register ...........................................................	C-57
17-15	Peripheral Interrupt Handler x Vector Base (PIHx_VEC_BASE) Registers ..............	C-58
C-32	Peripheral Interrupt Handler x Vector Index (PIHx_VEC_IDX) Registers .................	C-59
C-33	Processor Status Word (PSW) ..................................................................................	C-60
C-34	PTS Select (PTSSEL) Register .................................................................................	C-62
C-35	PTS Service (PTSSRV) Register ..............................................................................	C-63
C-36	PWM Count (PWMx_y_COUNT) Register ................................................................	C-64
C-37	PWM Period (PWMx_y_PERIOD) Register ..............................................................	C-64
C-38	PWM Control (PWMx_CONTROL, PWMy_CONTROL) Registers ...........................	C-65
C-39	Reset Source (RSTSRC) Register ............................................................................	C-66
C-40	Serial Port Receive Buffer (SBUF_RX) Register.......................................................	C-66
C-41	Stack Pointer (SP) .....................................................................................................	C-68

xvi

		CONTENTS
	FIGURES
Figure		Page
C-42 Serial Port x Baud Rate (SPx_BAUD) Register.........................................................		C-69
C-43 Serial Port Control (SPx_CON) Register...................................................................		C-70
C-44 Serial Port Status (SPx_STATUS) Register..............................................................		C-72
C-45 Synchronous Serial Port Baud (SSIO_BAUD) Register ............................................		C-74
C-46 Synchronous Serial x Buffer (SSIOx_BUF) Register.................................................		C-75
C-47 SSIO 0 Clock (SSIO0_CLK) Register........................................................................		C-75
C-48 SSIO 1 Clock (SSIO1_CLK) Register........................................................................		C-76
C-49 Synchronous Serial Control x (SSIOx_CON) Registers ............................................		C-79
C-50 Lower Stack Limit (STACK_BOTTOM) Register .......................................................		C-81
C-51	Upper Stack Limit (STACK_TOP) Register ...............................................................	C-82
C-52	Timer x Control (TxCONTROL) Register...................................................................	C-83
C-53	Timer x Time (TIMERx) Registers .............................................................................	C-85
C-54	Timer/Counter Multiplexer (TIMER_MUX) Register ..................................................	C-86

xvii