ARCHITECTURAL OVERVIEW

2.4INTERNAL TIMING

This section describes the internal clock circuitry and power management logic.

2.4.1Clock and Power Management Logic

The 8XC196EA’s clock circuitry (Figure 2-6) implements a phase-locked loop and clock multiplier, which can substantially increase the CPU clock rate while using a lower-frequency input clock.

FXTAL1

XTAL1

XTAL2

Disable Oscillator (Powerdown)

Disable

Phase

Filter

PLL

Comparator

(Powerdown)

Phase-locked

Oscillator

XTAL1

XTAL1

PLLEN

Phase-locked Loop

Clock Multiplier

F

2F

1

0

f

Disable Clock Input (Powerdown)

Divide by two

Circuit

	f/2		To reset logic
			Disable Clocks (Idle, Powerdown)
	Clock	Clock	CPU Clocks (PH1, PH2)
		Failure
	Generators
		Detection	Peripheral Clocks (PH1, PH2)
	f/2
	Programmable		OSC
	Divider
	(CLK1:0)
			0
		f	CLKOUT
			1
			Disable Clocks (Powerdown)
			A3378-01

Figure 2-5. Clock Circuitry

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