CHAPTER 6

STANDARD AND PTS INTERRUPTS

This microcontroller’s flexible interrupt-handling system has three main components: the programmable interrupt controller, the peripheral transaction server (PTS), and the peripheral interrupt handlers (PIHs). This chapter describes these components and explains how to program them.

6.1OVERVIEW OF THE INTERRUPT CONTROL CIRCUITRY

The interrupt control circuitry within a microcontroller permits real-time events to control program flow. When an event generates an interrupt, the microcontroller suspends the execution of current instructions while it performs some service in response to the interrupt. When the interrupt is serviced, program execution resumes at the point where the interrupt occurred. An internal peripheral, an external signal, or an instruction can generate an interrupt request. In the simplest case, the microcontroller receives the request, performs the service, and returns to the task that was interrupted.

The interrupt sources fall into two categories. The unimplemented opcode, software trap, and NMI interrupt sources are always enabled. All other sources can be individually enabled.

Interrupts that go through the interrupt controller are serviced by interrupt service routines that you provide (Figure 6-1). The lower 16 bits of the addresses of these interrupt service routines are stored in the upper and lower interrupt vectors in special-purpose memory (Table 4-2 on page 4-8). The CPU automatically adds FF0000H to the 16-bit vector in special-purpose memory to calculate the address of the interrupt service routine, and then executes the routine.

The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides high-speed, low-overhead interrupt handling; it does not modify the stack or the PSW. You can configure most interrupts (except NMI, software trap (TRAP), unimplemented opcode, stack overflow, PIH0_INT, and PIH1_INT) to be serviced by the PTS instead of the interrupt controller.

The PTS provides four special microcoded routines that enable it to complete specific tasks faster than an equivalent interrupt service routine. It can transfer bytes or words, either individually or in blocks, between any memory locations in page 00H; abort PTS service if a dummy PTS request occurs; and test for a missing event in a series of regular events. PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines.

A block of data called the PTS control block (PTSCB) contains the specific details for each PTS routine (see “Initializing the PTS Control Blocks” on page 6-30). When a PTS interrupt occurs, the priority resolver selects the appropriate vector from special-purpose memory and fetches the PTS control block (PTSCB).

To provide support for the large number of event processor array (EPA) channels, the 8XC196EA incorporates two peripheral interrupt handlers (PIHs). Each PIH services 16 different interrupt sources. You can select either interrupt controller or PTS service for each PIH interrupt source. When a PIH receives an interrupt request from an enabled source, it generates either a standard

6-1

8XC196EA USER’S MANUAL

interrupt request or PTS service request to the CPU. Although the PIH interrupt vectors are stored in special-purpose memory, the PIH must supply the interrupt vector address to the CPU.

	Unimplemented Opcode
				TRAP		Interrupt
				NMI †	NMI	Controller
		Stack Overflow †			Stack Overflow
					INT_PEND
				PIH1_INT
				PIH1_PTS	INT_PEND1
					Highest Priority Standard
EPA16	1		0		Interrupt Request
	Handler		Handler	PIH0_INT
OS7:0					INT_MASK
	Interrupt	(PIH1)	Interrupt	(PIH0) PIH0_PTS	Highest Priority PTS Request	PTS
OVRTM4:1	Peripheral		Peripheral
					INT_MASK1
OVR2:0
EPA15:0					PTSSEL
				SSIO1
				SSIO0
				SDU
		EXTINT			PTSSRV
				RI1
				TI1
			AD_DONE
			EPAx_OVR		Priority
				RI0	Resolver
				TI0
† The NMI and Stack Overflow interrupts cannot be masked and are always serviced by the
interrupt controller.
						A4305-01

Figure 6-1. Interrupt Structure Block Diagram

6-2

STANDARD AND PTS INTERRUPTS

Interrupt Pending or PTSSRV Bit Set

NMI or

Yes

Stack Overflow

Pending

?

No

No

INT_MASK.x

Return

No

= 1?

Interrupts

Enabled

Return

Yes

?

PTS

No

Yes

Enabled

?

PTSSEL.x

No

Yes

Bit = 0

?

PTSSEL.x

No

Yes

Bit = 1

?

Priority

Yes

Resolver

Highest Priority Interrupt

Priority

Resolver

Yes

No

Highest Priority PTS Interrupt

PTSSRV.x

= 1

?

Reset INT_PEND.x

Bit

Reset PTSSRV.x

Reset INT_PEND.x

Bit

Bit

Execute PTS Cycles

(Microcoded)

PUSH PC

on Stack

Clear PTSSEL.x Bit

LJMP to Interrupt

Service Routine

Set PTSSRV.x Bit

Execute Interrupt

Service Routine

Request end-of-PTS interrupt

POP PC

from Stack

Return

A4304-03

Figure 6-2. Interrupt Service Flow Diagram

6-3

8XC196EA USER’S MANUAL

6.2INTERRUPT SIGNALS AND REGISTERS

Table 6-1 describes the external interrupt signals and Table 6-2 describes the interrupt control and status registers.

			Table 6-1. Interrupt Signals
	Interrupt	Type	Description
	Signal
	EXTINT	I	External Interrupt
			In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending
			bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one
			state time.
			In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device
			to resume normal operation. The interrupt does not need to be enabled, but the pin
			must be configured as a special-function input. If the EXTINT interrupt is enabled, the
			CPU executes the interrupt service routine. Otherwise, the CPU executes the
			instruction that immediately follows the command that invoked the power-saving mode.
			In idle mode, asserting any enabled interrupt causes the device to resume normal
			operation.
			EXTINT shares a package pin with P2.2.
	NMI	I	Nonmaskable Interrupt
			In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt.
			NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one
			state time to guarantee that it is recognized.

Table 6-2. Interrupt and PTS Control and Status Registers

Mnemonic	Address	Description
INT_MASK	0008H	Interrupt Mask Registers
INT_MASK1	0013H	The bits in these registers enable or disable each maskable
		interrupt (that is, each interrupt except unimplemented opcode,
		software trap, NMI, and stack overflow).
INT_PEND	0009H	Interrupt Pending Registers
INT_PEND1	0012H	The bits in these registers are set by hardware to indicate that an
		interrupt is pending.
PIH0_INT_MASK	1E98H	Peripheral Interrupt Handler (PIH) Interrupt Mask Registers
PIH1_INT_MASK	1EA8H	The bits in these registers enable or disable each interrupt that is
		routed through the PIH.
PIH0_INT_PEND	1E9AH	Peripheral Interrupt Handler (PIH) Interrupt Pending Registers
PIH1_INT_PEND	1EAAH	The bits in these registers are set by hardware to indicate that a
		PIH interrupt source is pending.
PIH0_PTSSEL	1E96H	Peripheral Interrupt Handler (PIH) PTS Select Registers
PIH1_PTSSEL	1EA6H	These registers select either a PTS interrupt service request or a
		standard interrupt service request for each interrupt that is routed
		through the PIH.

6-4