8XC196EA USER’S MANUAL

Because the RISM begins at location FF2000H in serial port programming mode, the ROM locations are automatically remapped as shown in Table 17-4. For example, to access ROM location FF2000H in serial port mode, you must address it as FFA000H.

Table 17-4. Serial Port Mode Memory Map

			Address Range (Hex)
	Description
		Normal Operation	Serial Port Programming Mode
	Internal ROM	FF2000–FF3FFF	FFA000–FFBFFF
	External memory	—	FF4000–FF5FFF
	Do not address	—	FF2400–FF3FFF
	Test ROM and RISM	—	FF2000–FF23FF

17.6 SDU RISM EXECUTION ROUTINE

The SDU RISM execution routine contains a built-in reduced instruction set monitor (RISM), which enables you to access user routines that reside in test-ROM. The on-chip RISM commands are accessed via the SDU module (see Table 17-7 on page 17-15). To access the RISM routine, set the interrupt (SDU_INT) bit of the SDU command byte and program your software to vector to the RISM. (Refer to Figure 16-7 on page 16-8 for additional information on using the SDU command byte.)

NOTE

The SDU interrupt occurs at the execution of the SDU command byte. The mode select (SDU_COM.5:2) bits must not equal 00H or 0FH, or the reset SDU instruction will take precedence. Use 68H as the SDU command byte to generate an interrupt.

When accessing the SDU RISM execution routine, code RAM address locations 0400–0407H are reserved (see Figure 17-4) and must not be used in any user routines that are called. The eight bytes of the SDU RISM control block are used to communicate to the CPU, since the CPU has no direct access to any SDU register.

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USING THE TEST-ROM ROUTINES

SDU RISM Control Block

The SDU RISM control block contains data and address registers (RISM_DATA and RISM_ADDR) and a command byte register (RISM_COM) for initializing a data transfer.

		7		0
RISM_TEMP				Reserved
			7	0
RISM_TEMP
				Reserved
			15	8
RISM_DATA(H)				SDU RISM Data (high byte)
			7	0
RISM_DATA(L)				SDU RISM Data (low byte)
			23	16
RISM_ADDR(H)				SDU RISM Address (high byte)
			15	8
RISM_ADDR(M)
				SDU RISM Address (middle byte)
			7	0
RISM_ADDR(L)				SDU RISM Address (low byte)
			7	0
RISM_COM				SDU RISM Command Byte
Register		Address		Function
RISM_TEMP	407–406H			Reserved.
RISM_DATA		405–404H		SDU RISM Data
				Stores the data content to be written.
RISM_ADDR		403–401H		SDU RISM Address
				Stores the address to which the data content is to be read or written.
RISM_COM		400H		SDU RISM Command Byte
				See Table 17-7 on page 17-15 for the RISM commands supported by
				the SDU.

Figure 17-4. SDU RISM Control Block

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