MINIMUM HARDWARE CONSIDERATIONS

13.6.5 Detecting Clock Failure

The ability to sense a clock failure is important in safety-sensitive applications. This microcontroller provides a feature that can detect a failed clock and reset itself. Low-frequency oscillation, typically 100 kHz or below, is sensed as a failure. If enabled, the clock failure detection (CFD) circuitry resets the microcontroller in the event of a clock failure. This feature is enabled by programming the CFD bit in the chip configuration 1 (CCR1) register. (See Figure 2-10 on page 2-20 for details.)

13.7 IDENTIFYING THE RESET SOURCE

The reset source (RSTSRC) register indicates the sources of the last reset that the microcontroller encountered (see Figure 13-11). If more than one reset occurs at the same time, all of the corresponding RSTSRC bits will be set. Reading this SFR clears all the register bits.

RSTSRC									Address:	1FA4H
									Reset State:	00H†
The reset source (RSTSRC) register indicates the sources of the last reset that the microcontroller
encountered.
7										0
—		—	—		—		CFDRST	WDTRST	SFWRST	EXTRST
Bit		Bit					Function
Number		Mnemonic
7:4		—	Reserved. These bits are undefined.
3		CFDRST	Clock Failure Detection Reset
			When set, this bit indicates that a failed clock caused the last reset.
2		WDTRST	Watchdog Timer Reset
			When set, this bit indicates that the watchdog timer caused the last reset.
1		SFWRST	Software Reset
			When set, this bit indicates that either the RST instruction or the IDLPD
			instruction used with an illegal key caused the last reset.
0		EXTRST	External Reset
			When set, this bit indicates that the RESET# pin being asserted caused the
			last reset.

† Applies to VCC Powerup condition only.

Figure 13-11. Reset Source (RSTSRC) Register

13-13

14

Special Operating

Modes