8XC196EA USER’S MANUAL

8.3.2.4Multiprocessor Communications

Modes 2 and 3 are provided for multiprocessor communications. In mode 2, during receptions, the serial port sets the RI flag in SPx_STATUS and the RIx interrupt pending bit only when the ninth data bit received (SPx_STATUS.7, the RB8 bit) is a one. In mode 3, the serial port sets the RI flag and the RIx interrupt pending bit regardless of the value of the ninth data bit received.

One way to use these modes for multiprocessor communication is to set the master processor to mode 3 and the slave processors to mode 2. When the master processor wants to transmit a block of data to one of several slaves, it sends out an address frame that identifies the target slave. The ninth bit is always set in the address frame, so an address frame interrupts all slaves. Each slave examines the address byte to check whether it is being addressed. The addressed slave switches to mode 3 to receive the data frames, which are sent with the ninth bit cleared. The slaves that are not addressed continue to operate in mode 2, and therefore are not interrupted by the data frames, which are sent with the ninth data bit cleared.

8.4PROGRAMMING THE SERIAL PORT

To use the SIO port, you must configure the port pins to serve as special-function signals and set up the SIO channels.

8.4.1Configuring the Serial Port Pins

Before you can use the serial port, you must configure the associated port pins to serve as specialfunction signals. Table 8-1 on page 8-4 describes the pins associated with the serial port, Table 8-2 on page 8-4 describes the port configuration registers, and Table 8-3 explains how to configure the pins.

Table 8-3. Port Register Settings for the SIO Signals

	Signal	Configuration	Port Register
			Settings
	RXD0 (mode 0)	Input for receptions	P2_DIR.1 = 1
		Open-drain output for transmissions	P2_MODE.1 = 1
			(external pull-up required)
	RXD0 (modes 1, 2, and 3)	Input	P2_DIR.1 = 1
			P2_MODE.1 = 1
			P2_REG.1 = 1
	RXD1 (mode 0)	Input for receptions	P2_DIR.4 = 1
		Open-drain output for transmissions	P2_MODE.4 = 1
			(external pull-up required)
	RXD1 (modes 1, 2, and 3)	Input	P2_DIR4 = 1
			P2_MODE.4 = 1
			P2_REG.4 = 1

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			SERIAL I/O (SIO) PORT
	Table 8-3. Port Register Settings for the SIO Signals (Continued)
	Signal	Configuration	Port Register
			Settings
	T2CLK	Input	P7_DIR.2 = 1
			P7_MODE.2 = 1
			P7_REG.2 = 1
	TXD0	Complementary output	P2_DIR.0 = 0
			P2_MODE.0 = 1
	TXD1	Complementary output	P2_DIR.3 = 0
			P2_MODE.3 = 1

8.4.2Programming the Control Register

The SPx_CON register (Figure 8-6) selects the communication mode and enables or disables the receiver for all modes. For modes 1 and 3, SPx_CON enables or disables even or odd parity. For modes 2 and 3, SPx_CON contains the ninth data bit to be transmitted. Use this register to delay the setting of the TI and TXE flags in the serial port status register and the TIx interrupt pending bit by one, three, or seven bit times. Selecting a new mode stops any transmission or reception in progress on the channel.

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8XC196EA USER’S MANUAL

SPx_CON	Address:	1F8BH, 1F9BH
x = 0–1	Reset State:	00H

The serial port control (SPx_CON) register selects the communications mode and enables or disables the receiver for all modes. For modes 1 and 3, it enables or disables even or odd parity. For modes 2 and 3, it contains the ninth data bit to be transmitted. Use this register to delay the setting of the TI and TXE flags in the serial port status register and the TIx interrupt pending bit by one, three, or seven bit times.

7

0

ID1

ID0

PAR

TB8

REN

PEN

M1

M0

Bit

Bit

Function

Number

Mnemonic

7:6

ID1:0

Interrupt Delay

These bits delay the setting of the TI and TXE flags in the SPx_STATUS

register and the TIx interrupt pending bit after transmissions.

For mode 0, the SIO sets the TI and TXE flags and the TIx pending bit

immediately after it shifts out the eighth data bit unless a delay is selected.

For modes 1, 2, and 3, the SIO sets TI and TXE flags and the TIx pending

bit when it starts to shift out the stop bit unless a delay is selected.

ID1

ID0

0

0

set immediately (no delay)

0

1

delay by one bit time

1

0

delay by three bit times

1

1

delay by seven bit times

5

PAR

Parity Selection Bit

In modes 1 and 3, this bit selects even or odd parity.

0 = even parity

1 = odd parity

For modes 0 and 2, this bit is ignored.

4

TB8

Transmit Ninth Data Bit

This is the ninth data bit that will be transmitted in mode 2 or 3. This bit is

cleared after each transmission, so you must write to this bit before writing

to SBUFx_TX. For mode 3, when parity is enabled (SPx_CON.2 = 1), the

transmitter sets or clears this bit so that the byte being transmitted contains

the correct parity.

3

REN

Receive Enable

In mode 1, 2, or 3, setting this bit enables receptions. When this bit is set, a

falling edge on the RXDx pin starts a reception. In these modes, this bit has

no effect on transmissions.

In mode 0, clearing this bit enables transmissions and setting it enables

receptions.

Clearing this bit stops a reception in progress and inhibits further

receptions. In mode 0, clearing the RI flag in the SPx_STATUS register

starts a reception; therefore, to avoid corrupting your reception, clear this

bit before clearing the RI bit.

Figure 8-6. Serial Port Control (SPx_CON) Register

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SERIAL I/O (SIO) PORT

SPx_CON (Continued)	Address:	1F8BH, 1F9BH
x = 0–1	Reset State:	00H

The serial port control (SPx_CON) register selects the communications mode and enables or disables the receiver for all modes. For modes 1 and 3, it enables or disables even or odd parity. For modes 2 and 3, it contains the ninth data bit to be transmitted. Use this register to delay the setting of the TI and TXE flags in the serial port status register and the TIx interrupt pending bit by one, three, or seven bit times.

7

0

ID1

ID0

PAR

TB8

REN

PEN

M1

M0

Bit

Bit

Function

Number

Mnemonic

2

PEN

Parity Enable

In modes 1 and 3, setting this bit enables parity. For mode 1, when this bit

is set, the seventh data bit takes the parity value on transmissions and

SPx_STATUS.7 becomes the receiver parity error bit. For mode 3, when

this bit is set, SPx_CON.4 (TB8) takes the parity value on transmissions

and SPx_STATUS.7 becomes the receive parity error bit.

Clear this bit for mode 2.

For mode 0, this bit is ignored.

1:0

M1:0

Mode Selection

These bits select the communications mode.

M1

M0

0

0

mode 0, synchronous

0

1

mode 1, 8-bit asynchronous with optional parity

1

0

mode 2, 9-bit asynchronous with optional receive interrupt

1

1

mode 3, 9-bit asynchronous with optional parity

Figure 8-6. Serial Port Control (SPx_CON) Register (Continued)

8.4.3Programming the Baud Rate and Clock Source

The SPx_BAUD register (Figure 8-7) selects the clock input for the baud-rate generator and defines the baud rate for all serial I/O modes. For mode 0, this register determines the baud rate output on the serial clock pin (TXDx). For modes 1, 2, and 3, this register controls the transmit and receive shift clocks.

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8XC196EA USER’S MANUAL

SPx_BAUD	Address:	1F8CH, 1F9CH
x = 0–1	Reset State:	0000H

The serial port baud rate x (SPx_BAUD) register selects the clock source and serial port baud rate. The most-significant bit selects the clock source. The lower 15 bits represent baud value, an unsigned integer that determines the baud rate.

The maximum baud value is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum baud value is 0000H when using the internal clock source (f) and 0001H when using T2CLK. In synchronous mode 0, the minimum baud value is 0001H for transmissions and 0002H for receptions.

WARNING: Writing to the SPx_BAUD register during a reception or transmission can corrupt the received or transmitted data. Before writing to SPx_BAUD, check SPx_STATUS or the interrupt pending register to ensure that the reception or transmission is complete.

15

CLKSRC	BV14	BV13	BV12
7
BV7	BV6	BV5	BV4

8

BV11	BV10	BV9	BV8
			0
BV3	BV2	BV1	BV0

Bit	Bit			Function
Number	Mnemonic
15	CLKSRC	Serial Port Clock Source
		This bit determines whether the baud-rate generator is clocked from an
		internal or an external source.
		0 = signal on the T2CLK pin (external source)
		1 = internal operating frequency (f)
14:0	BV14:0	These bits constitute the baud value.
		Use the following equations to determine the baud value for a given baud
		rate.
		Synchronous mode 0:†
		Baud Value =	f	– 1	or	T2CLK
			------------------------------			---------------------------
			Baud Rate	× 2		Baud Rate
		Asynchronous modes 1, 2, and 3:
		Baud Value =	f	– 1	or	T2CLK
			------------------------------			Baud-------------------------------------Rate × 8
			Baud Rate	× 16
		† For mode 0 receptions, the baud value must be 0002H or greater. For
		mode 0 transmissions, the baud value must be 0001H or greater.

Figure 8-7. Serial Port x Baud Rate (SPx_BAUD) Register

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SERIAL I/O (SIO) PORT

NOTE

For mode 0 receptions, the baud value must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect.

The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXDx. Although these two signals are normally synchronized, the internal signal generates one clock before the first pulse transmitted by TXDx and this first clock signal is not synchronized with TXDx. This clock signal causes the receive shift register to shift in whatever data is present on the RXDx pin. This data is treated as the leastsignificant bit (LSB) of the reception. The reception then continues in the normal synchronous manner, but the data received is shifted left by one bit because of the false LSB. The seventh data bit transmitted is received as the most-significant bit (MSB), and the transmitted MSB is never shifted into the receive shift register.

Using the internal peripheral clock at 40 MHz, the maximum baud rate for mode 0 is 5.52 Mbaud. The maximum baud rate for modes 1, 2, and 3 is 2.0 Mbaud.

Table 8-4 shows the SPx_BAUD values for common baud rates when using a 40 MHz, internal peripheral clock. Because of rounding, the baud value formula is not exact and the resulting baud rate is slightly different than desired. The tables show the percentage of error when using the sample SPx_BAUD values. In most cases, a serial link will work with up to a 5.0% difference in the receiving and transmitting baud rates.

Table 8-4. SPx_BAUD Values When Using the Internal Clock at 40 MHz

Baud Rate	SPx_BAUD Register Value†			% Error
	Mode 0	Mode 1, 2, 3	Mode 0		Mode 1, 2, 3
19200	8411H	8081H	–0.04		+0.16
9600	8822H	8103H	+0.02		+0.16
4800	9046H	8208H	–0.01		–0.04
2400	A080H	8411H	+0.01		–0.04
1200	C11AH	8822H	–0.01		+0.02

†Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud-rate generator.

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