8XC196EA USER’S MANUAL

14.4 POWERDOWN MODE

Powerdown mode places the microcontroller into a very low power state by disabling the internal oscillator, the phase-locked loop circuitry, and the clock generators. Internal logic holds the CPU and peripheral clocks at logic zero, which causes the CPU to stop executing instructions, the system bus-control signals to become inactive, the CLKOUT signal to become high, and the peripherals to turn off. Power consumption drops into the microwatt range (refer to the datasheet for exact specifications). ICC is reduced to device leakage. Table B-5 on page B-15 lists the values of the pins during powerdown mode. If VCC is maintained above the minimum specification, the spe- cial-function registers (SFRs) and register RAM retain their data.

14.4.1 Enabling and Disabling Powerdown Mode

The PD bit in the chip configuration register 0 (CCR0.0) either enables or disables both idle and powerdown modes. CCR0 cannot be accessed by code; the PD bit value is defined in chip configuration byte 0 (CCB0.0). If the PD bit is set, both idle and powerdown modes are enabled. If the PD bit is clear, both are disabled. CCR0 is loaded from CCB0 when the microcontroller returns from reset.

14.4.2 Entering Powerdown Mode

Before entering powerdown, complete the following tasks:

•Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received.

•Put all other peripherals into an inactive state.

After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode.

NOTE

To prevent an accidental return to full power, hold the external interrupt pin (EXTINT) low while the device is in powerdown mode.

14.4.3 Exiting Powerdown Mode

The microcontroller will exit powerdown mode when either of the following events occurs:

•a hardware reset is generated

•a transition occurs on the external interrupt pin

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SPECIAL OPERATING MODES

14.4.3.1Generating a Hardware Reset

The microcontroller will exit powerdown if RESET# is asserted. Asserting RESET# causes the chip to reset and return to normal operating mode. If the phase-locked loop (PLL) clock circuitry is enabled or if the design uses an external clock input signal, you must hold RESET# low for at least 2 ms to allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled. If the design uses the on-chip oscillator, then either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times.

14.4.3.2Asserting the External Interrupt Signal

The other way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a level-sensitive input. An interrupt does not need to be enabled to bring the microcontroller out of powerdown, but the pin must be configured as a special-function input (see “Configuring the Port Pins” on page 7-7). Figure 14-2 shows the power-up and power-down sequence when using an external interrupt to exit powerdown.

When the external interrupt brings the microcontroller out of powerdown mode, the corresponding pending bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the interrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruction. If the interrupt is disabled (masked), the device fetches and executes the instruction following the IDLPD #2 instruction, and the pending bit remains set until the interrupt is serviced or software clears the pending bit.

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8XC196EA USER’S MANUAL

XTAL1

CLKOUT

PH1

Internal Powerdown

Signal

EXTINT

RPD

Timeout (Internal)

A3410-01

Figure 14-2. Power-up and Power-down Sequence When Using an External Interrupt

When using the external interrupt signal to exit powerdown mode, we recommend that you connect the external capacitor shown in Figure 14-3 to the RPD pin. The discharging of the capacitor causes a delay that allows the oscillator and phase-locked loop (PLL) circuitry to stabilize before the internal CPU and peripheral clocks are enabled.

MCS®96

Microcontroller

RPD

C1

A2389-02

Figure 14-3. External RC Circuit

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SPECIAL OPERATING MODES

During normal operation (before entering powerdown mode), an internal pull-up holds the RPD pin at VCC. When the external interrupt signal is asserted, the internal oscillator circuitry is enabled and turns on a weak internal pull-down (approximately 10 kΩ). This weak pull-down causes the external capacitor (C1) to begin discharging at a typical rate of 200 μA. When the RPD pin voltage drops below the threshold voltage (about 2.5 V), the internal phase clocks are enabled and the device resumes code execution.

At this time, a Schmitt-triggered detection circuit prompted by the switching voltage levels strongly drives a logic one, quickly pulling the RPD pin back up to VCC (see recovery time in Figure 14-4). The time constant (RC) follows an exponential charging curve. However, since there is no external resistor on the RPD pin, the time constant goes to zero and the recovery time is instantaneous.

Vc	= Vcc[ 1 – e(t ¤ t) ] ; ( τ = RC1 = 0)
Vc	= Vcc

where:

VC = Charging capacitor voltage

14.4.3.3 Selecting an External Capacitor

With the resistance of the discharge path designed into the silicon with an internal pull-down resistor, the selection of an external capacitor (C1) can be critical. Ideally, you want to select a component that will produce a sufficient discharge time to permit the internal oscillator circuitry to stabilize. Because many factors can influence the discharge time requirement, you should always fully characterize your design under worst-case conditions to verify proper operation.

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8XC196EA USER’S MANUAL
5						5 V
4	EXTINT
3						3 V
RPD, Volts
2
1	200 μA C1 Discharge							1.2 V
								.8 V
				Code Execution
					Resumes
	2	4	6	8	10	12	14	16	18	20	22
					Time, ms
		Vcc = 5 V
		Vcc = 3 V
											A3411-01

Figure 14-4. Typical Voltage on the RPD Pin While Exiting Powerdown

When selecting the capacitor, determine the worst-case discharge time needed for the oscillator to stabilize, then use this formula to calculate an appropriate value for C1.

TDIS × I

C1 = -------------------

Vt

where:

C1	is the capacitor value, in farads
TDIS	is the worst-case discharge time, in seconds
I	is the discharge current, in amperes
Vt	is the threshold voltage

NOTE

If powerdown is re-entered and exited before C1 charges to VCC, it will take less time for the voltage to ramp down to the threshold. Therefore, the device will take less time to exit powerdown.

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