SYNCHRONOUS SERIAL I/O (SSIO) PORT

9.5PROGRAMMING CONSIDERATIONS

The following sections discuss some considerations for programming the SSIO port.

9.5.1Variable-width MSB

For transmissions, the time that you write to SSIOx_BUF determines the data setup time (the length of time between data being placed on the data pin and the first clock edge on the clock pin). The reason for this anomaly is that the baud-rate down-counter starts when you write to SSIO_BAUD, but the transmission does not start until you write to SSIO x_BUF. The write to SSIOx_BUF can occur at any point during the count. Since the most-significant bit (MSB) does not change until the selected shift edge of SCx, the width of the MSB appears to vary (Figure 9-12). If you write to SSIOx_BUF early in the count, the MSB seems relatively long. If you write to SSIOx_BUF late in the count, the MSB seems relatively short.

For example, assume that you write 93H to SSIO_BAUD (the MSB enables the baud-rate generator, and the lower seven bits define the initial count value) and program the SSIO to shift out data on falling SCx edges. Also, assume an internal operating frequency of 32 MHz. As soon as you write SSIO_BAUD, the down-counter starts decrementing from 13H. (The baud-rate downcounter decrements every four state times and a state time is equal to 2/f, where f is the internal operating frequency.) If the counter is at 11H when you write to SSIOx_BUF, the MSB remains on the data pin for approximately 4.25 µs (17 × 4 × 2/(32 × 106)). If the counter is at 03H when you write to SSIOx_BUF, the MSB remains on the data pin for only approximately 0.75 µs (3 × 4 × 2/(32 × 106)).

Clock (SCx pin)

1

2

3

4

"1" "0" "1" "0" "0"

MSB

B6

B5

B4

B3

Data (SDx pin)

A2066-01

Figure 9-12. Variable-width MSB in SSIO Transmissions

NOTE

This condition exists only for the MSB. Once the MSB is clocked out, the remaining bits are clocked out consistently at the programmed frequency.

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8XC196EA USER’S MANUAL

One way to achieve a consistent MSB bit length is to start the down-count at a fixed time, using these steps: (Assume ATR bit is set.)

1.Clear SSIO_BAUD bit 7. This disables the baud-rate generator and clears the remaining bits (BV6:0).

2.Disable interrupts.

3.Write the byte to be transmitted to SSIOx_BUF.

4.Set the MSB of SSIO_BAUD and write the desired baud value to the remaining bits. This enables the baud-rate generator and starts the down count.

5.Enable interrupts.

Using this procedure starts the clock at a known point before each transmission, establishing a predictable MSB bit time.

9.5.2Standard Mode Considerations

For standard operations, the serial channels function as two independent channels. SSIO_BAUD enables the baud-rate generator and defines the baud rate for the baud clock. When either channel is configured as master, its serial clock is synchronized with the baud clock during transfers. Use SSIO1_CLK to select standard mode. Use SSIO0_CON, SSIO0_CLK, and SSIO0_BUF for configuring channel 0. Likewise, use SSIO1_CON, SSIO1_CLK, and SSIO1_BUF for configuring channel 1.

9.5.3Duplex Mode Considerations

For duplex operations, the serial channels function as a pair with SC0 as the common clock signal. However, PHAS and POLS bits in the SSIO0_CLK and SSIO1_CLK registers still affect the internal clocking of channel 0 and channel 1, respectively. Therefore, these bits should be set accordingly for each channel. Use SSIO1_CLK to select duplex mode. In duplex mode, the paired channels can function as master or slave. Use SSIO0_CON to configure the channel pair as master or slave. For master operations, use SSIO_BAUD to enable the baud-rate generator and define the baud clock. In this mode, channel 0’s clock signal is internally connected to channel 1’s serial clock signal; therefore, you must configure channel 1 as a slave, using SSIO1_CON. This allows serial clock 0 to be input on serial clock 1.

Additionally, for duplex operations, configure channel 0 as a transmitter and channel 1 as a receiver, using SSIO0_CON and SSIO1_CON. At the completion of a transfer, always read SSIO1_BUF before writing SSIO0_BUF to avoid losing the received data in SSIO1_BUF. When the channels are enabled, writing SSIO0_BUF starts a transmission; therefore, writing SSIO0_BUF before reading SSIO1_BUF would cause SSIO1_BUF to be overwritten with the new reception.

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SYNCHRONOUS SERIAL I/O (SSIO) PORT

9.5.4Channel-select Mode Considerations

For channel-select operations, the serial channels function as a pair with SC0 as the common clock signal. Use SSIO0_CON to configure the channel pair as master or slave. For master operations, use SSIO_BAUD to enable the baud-rate generator and define the baud clock. In this mode, channel 0’s clock signal is internally connected to channel 1’s serial clock signal; therefore, you must configure channel 1 as a slave, using SSIO1_CON. This allows serial clock 0 to be input on serial clock 1. Since SC0 is the common clock, use SSIO0_CLK to configure the clock signal.

Use SSIO1_CON to select either full-duplex or half-duplex channel-select operations. Full-du- plex operations use both serial data signals (SD0 and SD1), while half-duplex operations use only one serial data signal (SD1). As for duplex operations, for channel-select full-duplex operations, configure channel 0 as a transmitter and channel 1 as a receiver, using SSIO0_CON and SSIO1_CON. At the completion of a transfer, always read SSIO1_BUF before writing SSIO0_BUF to avoid losing the data in SSIO1_BUF. When the channels are enabled, writing SSIO0_BUF starts a transmission; therefore, writing SSIO0_BUF before reading SSIO1_BUF would cause SSIO1_BUF to be overwritten with the new reception.

Since channel-select half-duplex operations use serial clock 0 (SC0) and serial data 1 (SD1), you must write both control registers and both clock registers for these operations. SSIO0_CON configures SC0 for master or slave operations. SSIO1_CON configures SD1 for transmissions or receptions. SSIO0_CLK configures SC0; it selects the clock’s idle state and the clock edges on which the SSIO shifts out or samples data bits. Use SSIO1_CLK to configure the internal SC0 clock to channel 1, select channel-select half-duplex operations and enable or disable the master contention interrupt request.

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Pulse-width

Modulator