8XC196EA USER’S MANUAL

The RALU accesses the upper and lower register files differently. The lower register file is always directly accessible with direct addressing (see “Programming Considerations” on page 3-1). The upper register file is accessible with direct addressing only when windowing is enabled. Otherwise, the upper register file is accessed indirectly, through the memory controller. Windowing is a technique that maps blocks of the upper register file into a window in the lower register file. See Chapter 4, “Memory Partitions,”for more information about the register file and windowing.

2.3.2Memory Controller

The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory controller except when windowing is used; see Chapter 4, “Memory Partitions,”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, the bus controller, and the chip-select unit.

The bus controller drives the memory bus, which consists of an internal memory bus and the external bus. The bus controller receives memory-access requests from either the RALU or the prefetch queue; queue requests always have priority. This queue is transparent to the RALU and your software.

NOTE

When using a logic analyzer to debug code, remember that instructions are preloaded into the prefetch queue and are not necessarily executed immediately after they are fetched.

When the bus controller receives a request from the queue, it fetches the code from the address contained in the slave PC. The slave PC increases execution speed because the next instruction byte is available immediately and the processor need not wait for the master PC to send the address to the memory controller. If a jump, interrupt, call, or return changes the address sequence, the master PC loads the new address into the slave PC, then the CPU flushes the queue and continues processing.

The memory controller includes a chip-select unit with three chip-select outputs for selecting an external device during an external bus cycle. During an external memory access, a chip-select output is asserted if the address falls within the address range assigned to that chip-select. The bus width, the number of wait states, and multiplexed or demultiplexed address/data lines are programmed independently for the chip-selects. The address range of the chip-selects can be programmed for various granularities: 256 bytes, 512 bytes, … 512 Kbytes, or 2 Mbytes. The base address can be any address that is evenly divisible by the selected address range. See Chapter 15, “Interfacing with External Memory,” for more information.

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