8XC196EA USER’S MANUAL

nels or a single pair of output/simulcapture channels. You can use any number of pairs of adjacent capture/compare or adjacent output/simulcapture channels.

EPAx			EPAx
EPAy			EPAy
OSx			OSx
OSy			OSy

A4342-01

Figure 11-9. Controlling a Pair of Adjacent Pins

You might need to generate two edges that occur too close together to be generated by a single EPA channel (see Figure 11-10). To set up this configuration, you must program two EPAx_CON or OSx_CON registers for adjacent channels.

OS1			OS1
OS0			OS0
			(can remain as a general-purpose I/O signal)
			A4362-01

Figure 11-10. Generating Two Edges on One Pin

For example, you could configure OS0 to generate a falling edge and OS1 to generate a rising edge on the same pin. You can accomplish this by programming OS0_CON to 0600H and OS1_CON to 0440H, and using timer 1 as the time base.

11.5 PROGRAMMING THE EPA AND TIMER/COUNTERS

This section discusses configuring the port pins for the EPA and the timer/counters; describes how to program the timers, the capture/compare channels, and the compare-only (output/simulcapture) channels; and explains how to enable the EPA interrupts.

11-14

EVENT PROCESSOR ARRAY (EPA)

11.5.1 Configuring the EPA and Timer/Counter Signals

Before you can use the EPA, you must configure the appropriate port signals to serve as the spe- cial-function signals for the EPA and, optionally, for the timer/counter clock source and direction control signals. See “Configuring the Port Pins” on page 7-7 for information about configuring the ports.

Table 11-1 on page 11-2 lists the signals associated with the EPA and the timer/counters. Signals that are not being used for an EPA channel or timer/counter can be configured as general-purpose I/O signals.

11.5.2 Programming the Timers

The control registers for the timers are TxCONTROL (Figure 11-11) and TIMER_MUX (Figure 11-12). Write to these registers to configure the timers. Write to the TIMERx registers (Figure 11-13) to load a specific timer value.

TxCONTROL	Address:	Table 11-2
x = 1–4	Reset State:	0000H

The timer x control (TxCONTROL) register enables the associated timer/counter and specifies the counting direction, concatenation, reset source, clock source, and count rate for timer x.

15											8
—		—		—		—		—	—	CE	UD
7											0
ETC†		RM1		RM0		CM1		CM0	P2	P1	P0
15:10	—		Reserved; always write as zeros.
9	CE		Counter Enable
			This bit enables or disables the timer. From reset, the timers are disabled
			and not free running.
			0	= disable timer/counter
			1	= enable timer/counter
8	UD		Up/Down
			This bit specifies the timer’s counting direction.
			0	= count down
			1	= count up
			If T2CONTROL.7 is set, this bit in T1CONTROL controls the direction of
			both timers 2 and 1.
			If T4CONTROL.7 is set, this bit in T3CONTROL controls the direction of
			both timers 4 and 3.

† For T1CONTROL and T3CONTROL, this bit is reserved. Write zero to this bit for proper operation.

Figure 11-11. Timer x Control (TxCONTROL) Register

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8XC196EA USER’S MANUAL

TxCONTROL (Continued)	Address:	Table 11-2
x = 1–4	Reset State:	0000H

The timer x control (TxCONTROL) register enables the associated timer/counter and specifies the counting direction, concatenation, reset source, clock source, and count rate for timer x.

15

—	—	—	—
7
ETC†	RM1	RM0	CM1

8

—	—	CE	UD
			0
CM0	P2	P1	P0

7	ETC†	Enable Timer Concatenation
		This bit allows you to concatenate timers 2 and 1 and timers 4 and 3 to
		provide two 32-bit time bases.
		0	= no concatenation
		1	= concatenate timers
		Set this bit in T2CONTROL to concatenate timers 1 and 2.
		Set this bit in T4CONTROL to concatenate timers 3 and 4.
6:5	RM1:0	Reset Mode
		This bit specifies whether an output event causes a reset and, if so, the
		edge (falling, rising, or either) that causes the reset.
		RM1 RM0		Reset
		0	0	internal reset only
		0	1	reset reference timer x on falling edge
		1	0	reset reference timer x on rising edge
		1	1	reset reference timer x on falling or rising edge

† For T1CONTROL and T3CONTROL, this bit is reserved. Write zero to this bit for proper operation.

Figure 11-11. Timer x Control (TxCONTROL) Register (Continued)

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EVENT PROCESSOR ARRAY (EPA)

TxCONTROL (Continued)	Address:	Table 11-2
x = 1–4	Reset State:	0000H

The timer x control (TxCONTROL) register enables the associated timer/counter and specifies the counting direction, concatenation, reset source, clock source, and count rate for timer x.

15

—	—	—	—
7
ETC†	RM1	RM0	CM1

8

—	—	CE	UD
			0
CM0	P2	P1	P0

4:3	CM1:0	Clock Mode Select
		These bits specify whether the clock signal is provided by the internal
		frequency (f) or an external pin (TxCLK)
		CM1		CM0	Clocking
		0		0	internal clocking (f)
		0		1	external clocking on falling edge of TxCLK
		1		0	external clocking on rising edge of TxCLK
		1		1	external clocking on falling and rising edges of TxCLK
2:0	P2:0	EPA Clock Prescaler Bits
		These bits determine the clock prescaler value.
		P2		P1	P0	Prescaler Divisor	Resolution††
		0		0	0	divide by 1 (disabled)	100 ns
		0		0	1	divide by 2	200 ns
		0		1	0	divide by 4	400 ns
		0		1	1	divide by 8	800 ns
		1		0	0	divide by 16	1.6 µs
		1		0	1	divide by 32	3.2 µs
		1		1	0	divide by 64	6.4 µs
		1		1	1	—	reserved
		††	At f = 40 MHz and TIMER_MUX.0 = 0, use the formula on page 11-8 to
			calculate the resolution at other frequencies or with TIMER_MUX.0 =1.

† For T1CONTROL and T3CONTROL, this bit is reserved. Write zero to this bit for proper operation.

Figure 11-11. Timer x Control (TxCONTROL) Register (Continued)

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8XC196EA USER’S MANUAL

TIMER_MUX	Address:	1F6EH
	Reset State:	00H

The timer multiplexing (TIMER_MUX) register controls the number of timer values that can be timemultiplexed on the bus and available to the EPA for capture/compare or. With a two-state time field, only timers 1 and 2 can be used, and each timer’s maximum count rate is f/4. With a four-state time field, all four timers can be used, and each timer’s maximum count rate is f/8.

7

0

—

—

—

—

—

—

—

MXS

Bit

Bit

Function

Number

Mnemonic

7:1

—

Reserved; always write as zeros.

0

MXS

MUX Select

Selects a two-state or a four-state time field.

0 = two-state time field; timers 1 and 2 share the time bus, so each

of them can count every two state times (timers 3 and 4 cannot

be used)

1 = four-state time field; timers 1 through 4 share the time bus, so each

timer can count every four state times

Figure 11-12. Timer/Counter Multiplexer (TIMER_MUX) Register

TIMERx

Address:

Table 11-2

x = 1–4

Reset State:

0000H

This register contains the value of timer x. This register can be written, allowing timer x to be initialized to a value other than zero.

	15	0
		Timer Value
	Bit	Function
	Number
	15:0	Timer Value
		Read the current timer x value from this register or write a new timer x value to this
		register.
		Figure 11-13. Timer x Time (TIMERx) Registers

11-18