STANDARD AND PTS INTERRUPTS

6.3.1PIH Interrupt Sources, Priorities, and Vector Addresses

Tables 6-4 and 6-5 list the interrupt sources for the peripheral interrupt handler (PIH) interrupts with relative priority within the PIH and vector addresses. Each PIH provides the capability to handle 16 additional interrupt sources.

A major difference between PIH interrupts and interrupts that go directly to the CPU is that the PIH must provide the address of the individual PIH interrupt vector to the CPU. It can provide the address in one of two ways. Either your code can read the vector index register (PIHx_VEC_IDX, Figure 6-3 on page 6-8) directly, or the CPU can request the address as part of an interrupt acknowledge cycle.

Table 6-4. PIH0 Interrupt Sources, Vectors, and Priorities

			Interrupt
			Controller	PTS Service	PIH0
	Interrupt Source	Mnemonic	Service	(PIH0_PTS)
					Priority†
			(PIH0_INT)	Vector
			Vector
	EPA Capture/Compare 15	EPA15	FF20FCH	FF20FEH	15
	EPA Capture/Compare 14	EPA14	FF20F8H	FF20FAH	14
	EPA Capture/Compare 13	EPA13	FF20F4H	FF20F6H	13
	EPA Capture/Compare 12	EPA12	FF20F0H	FF20F2H	12
	EPA Capture/Compare 11	EPA11	FF20ECH	FF20EEH	11
	EPA Capture/Compare 10	EPA10	FF20E8H	FF20EAH	10
	EPA Capture/Compare 9	EPA9	FF20E4H	FF20E6H	9
	EPA Capture/Compare 8	EPA8	FF20E0H	FF20E2H	8
	EPA Capture/Compare 7	EPA7	FF20DCH	FF20DEH	7
	EPA Capture/Compare 6	EPA6	FF20D8H	FF20DAH	6
	EPA Capture/Compare 5	EPA5	FF20D4H	FF20D6H	5
	EPA Capture/Compare 4	EPA4	FF20D0H	FF20D2H	4
	EPA Capture/Compare 3	EPA3	FF20CCH	FF20CEH	3
	EPA Capture/Compare 2	EPA2	FF20C8H	FF20CAH	2
	EPA Capture/Compare 1	EPA1	FF20C4H	FF20C6H	1
	EPA Capture/Compare 0	EPA0	FF20C0H	FF20C2H	0

† The higher the number, the higher the priority.

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8XC196EA USER’S MANUAL

Table 6-5. PIH1 Interrupt Sources, Vectors, and Priorities

			Interrupt
			Controller	PTS Service	PIH1†
	Interrupt Source	Mnemonic	Service	(PIH1_PTS)
					Priority
			(PIH1_INT)	Vector
			Vector
	EPA Capture/Compare 16	EPA16	FF213CH	FF213EH	15
	Output Simulcapture 7	OS7	FF2138H	FF213AH	14
	Output Simulcapture 6	OS6	FF2134H	FF2136H	13
	Output Simulcapture 5	OS5	FF2130H	FF2132H	12
	Output Simulcapture 4	OS4	FF212CH	FF212EH	11
	Output Simulcapture 3	OS3	FF2128H	FF212AH	10
	Output Simulcapture 2	OS2	FF2124H	FF2126H	9
	Output Simulcapture 1	OS1	FF2120H	FF2122H	8
	Output Simulcapture 0	OS0	FF211CH	FF211EH	7
	Timer 1 Overflow/Underflow	OVRTM1	FF2118H	FF211AH	6
	Timer 2 Overflow/Underflow	OVRTM2	FF2114H	FF2116H	5
	Timer 3 Overflow/Underflow	OVRTM3	FF2110H	FF2112H	4
	Timer 4 Overflow/Underflow	OVRTM4	FF210CH	FF210EH	3
	EPA0 Capture Overrun	OVR0	FF2108H	FF210AH	2
	EPA1 Capture Overrun	OVR1	FF2104H	FF2106H	1
	EPA2 Capture Overrun	OVR2	FF2100H	FF2102H	0

† The higher the number, the higher the priority.

PIHx_VEC_IDX	Address:	1E90H, 1EA0H
x = 0–1	Reset State:	10H

The peripheral interrupt handler vector index (PIHx_VEC_IDX) registers indicate which standard PIH input is requesting interrupt service.

15

—	—	—	—
7
—	—	—	NI

8

—	—	—	—
			0
IS3	IS2	IS1	IS0

Bit		Bit	Function
Number		Mnemonic
15:5	—		Reserved. These bits are undefined.

Figure 6-3. Peripheral Interrupt Handler x Vector Index (PIHx_VEC_IDX) Registers

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STANDARD AND PTS INTERRUPTS

PIHx_VEC_IDX (Continued)	Address:	1E90H, 1EA0H
x = 0–1	Reset State:	10H

The peripheral interrupt handler vector index (PIHx_VEC_IDX) registers indicate which standard PIH input is requesting interrupt service.

15											8
—	—		—	—		—		—	—		—
7											0
—	—		—	NI		IS3		IS2	IS1		IS0
Bit	Bit						Function
Number	Mnemonic
4	NI		No Interrupt Pending
			This bit is set when the last PIHx interrupt request is serviced.
3:0	IS3:0		Interrupt Source
			These bits indicate the hex value of the highest-priority pending,
			standard PIHx interrupt request. PTS interrupt requests are not recorded
			in this register.

Figure 6-3. Peripheral Interrupt Handler x Vector Index (PIHx_VEC_IDX) Registers

6.3.1.1Using Software to Provide the Vector Address

This method works only when the PIH generates a standard interrupt request. If software reads the PIHx_VEC_IDX register directly, the highest-priority unmasked, standard interrupt is read and hardware clears the appropriate PIHx_INT_PEND and PIHx_PTSSRV bits. The value seen by software will be in one of two formats.

If no interrupt is active, the PIHx_VEC_IDX always contains 0010H:

0000 0000 0001 0000

If an interrupt is active, the PIHx_VEC_IDX register contains the following information:

0000 0000 0000 xxxx

where:

xxxx is the hex value of the highest priority interrupt pending

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8XC196EA USER’S MANUAL

For example, if both the EPA3 (priority 3) and EPA10 (priority 10) interrupts are pending in PIH0, the PIH0_VEC_IDX register contains 000AH, the value of the highest-priority pending interrupt:

0000 0000 0000 1010

Hardware clears the interrupt pending bit for EPA10 (PIH0_INT_PEND.10) and software services the EPA10 interrupt. When software reads the PIH0_VEC_IDX register a second time, it now contains 0003H, the value of the current highest-priority pending interrupt:

0000 0000 0000 0011

Hardware clears the interrupt pending bit for EPA3 (PIH0_INT_PEND.3) and software services the EPA3 interrupt. If software reads the register after the EPA3 interrupt is serviced, it now contains 0010H:

0000 0000 0001 0000

which indicates that there are no pending PIH0 interrupt requests.

The TIJMP instruction can be used to supply the interrupt vector addresses to the CPU. (See Appendix A for additional information about TIJMP.)

The format for the TIJMP instruction is:

TIJMP tbase,[index],#index_mask

where:
tbase	is a word register containing the 16-bit starting address of the jump
	table, which must be located in page FFH.
[index]	is a word register containing a 16-bit address that points to a register
	that contains a 7-bit value used to calculate the offset into the jump
	table.
#index_mask	is 7-bit immediate data to mask the index. This value is ANDed with
	the 7-bit value pointed to by [index] and the instruction multiplies
	the result by two to determine the offset into the jump table.

TIJMP calculates the destination address as follows:

([index] AND #index_mask) × 2 + tbase

To use the TIJMP instruction in this application, you would create a jump table with 17 destination addresses: one for each of the 16 standard PIHx interrupt sources and one for the return. The table must contain the lower 16 bits of each destination address. The TIJMP instruction will automatically add FF0000H to the destination address.

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