8XC196EA USER’S MANUAL

Table 11-2. EPA Control and Status Registers (Continued)

	Mnemonic	Address	Description
	PIH0_PTSSEL	1E96H	Peripheral Interrupt Handler (PIH) PTS Select
	PIH1_PTSSEL	1EA6H	These registers select either a PTS interrupt service request
			or a standard interrupt service request for each interrupt that
			is routed through the PIH.
	PIH0_PTSSRV	1E94H	Peripheral Interrupt Handler (PIH) PTS Service
	PIH1_PTSSRV	1EA4H	The bits in these registers are set by hardware to request an
			end-of-PTS interrupt.
	PIH0_VEC_BASE	1E92H	Peripheral Interrupt Handler (PIH) Vector Base Address
	PIH1_VEC_BASE	1EA2H	These registers contain the upper ten bits of the PIH interrupt
			vector address.
	PIH0_VEC_IDX	1E90H	Peripheral Interrupt Handler Vector Index Address
	PIH1_VEC_IDX	1EA0H	These registers contain the number of the highest priority
			active PIH interrupt request.
	T1CONTROL	1F7CH	Timer x Control
	T2CONTROL	1F78H	This register enables and disables timer x, controls whether it
	T3CONTROL	1F74H
			counts up or down, optionally concatenates two timers to
	T4CONTROL	1F70H
			create a 32-bit time base (timer 2 with timer 1 or timer 4 with
			timer 3 only), selects the clock source and direction, and
			determines the clock prescaler setting.
	TIMER1	1F7EH	Timer x Value
	TIMER2	1F7AH	This register contains the current value of timer x.
	TIMER3	1F76H
	TIMER4	1F72H
	TIMER_MUX	1F6EH	Timer Multiplexing Control
			This register controls the number of timer values that can be
			time-multiplexed on the bus and available to the EPA
			channels for capture/compare.

11.3 TIMER/COUNTER FUNCTIONAL OVERVIEW

The EPA has four up/down timer/counters, timer 1 through timer 4, which can be clocked internally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked externally. Figure 11-2 illustrates the timer/counter structure for timers 1 and 2. Timers 3 and 4 have an identical structure.

11-6

EVENT PROCESSOR ARRAY (EPA)

T2CONTROL.4:3

T2CONTROL.2:0

T2CONTROL.7

T2CONTROL.9

T2CLK

Enable

Prescaler

Internal

Module

Clock

Underflow/

Clock

Overflow

Signal

T2CONTROL.8

Direction

Reset

T2CONTROL.6:5

Internal Reset

T1CONTROL.4:3

T2RST

T1CONTROL.2:0

T1CONTROL.9

T1CLK

Enable

Prescaler

Clock

Internal Clock

Module

Underflow/

Signal

Overflow

T1CONTROL.8

Direction

Reset

T1CONTROL.6:5

Internal Reset

T1RST

OVRTM2

Interrupt

OVRTM1

Interrupt

A5021-02

Figure 11-2. EPA Timer/Counters

11-7

8XC196EA USER’S MANUAL

The timer/counters can be used as time bases for input captures, output compares, and programmed interrupts (software timers). When a counter increments from FFFEH to FFFFH or decrements from 0001H to 0000h, the counter-overflow/underflow interrupt pending bit is set. This bit can optionally cause an interrupt. The clock source, count direction, and resolution of the input capture or output compare are all programmable (see “Programming the Timers” on page 11-15). The maximum count rate is determined by the TIMER_MUX register. With a two-state time field, the maximum count rate is one-fourth the internal clock frequency (f/4); with a four-state time field, it is one-fourth the internal clock frequency (f/8). This provides a minimum resolution for an input capture or output compare of 100 ns (at f = 40 MHz).

resolution	4 × prescaler_divisor	8 × prescaler_divisor
	= ----------------------------------------------------------	or ----------------------------------------------------------
	f	f

where:

4	is the multiplier for TIMER_MUX.0 = 0 (timers 1 and 2 count every two state times).
8	is the multiplier for TIMER_MUX.0 = 1 (timers 1–4 count every four state times).
prescaler_divisor	is the clock prescaler divisor from the TxCONTROL registers (see
	“Programming the Timers” on page 11-15).
f	is the internal clock frequency. See “Internal Timing” on page 2-9 for details.

11.3.1 Timer Multiplexing on the Time Bus

You can use all four timers, in which case each timer can change value every four state times, or you can use just two timers, in which case timers 1 and 2 can change value every two state times and timers 3 and 4 cannot be used. The TIMER_MUX register (Figure 11-12 on page 11-18) controls the number of timers on the time bus. Figure 11-3 illustrates the two options.

TIMER _MUX.0 = 0
Time Bus	Timer 2	Timer 1	Timer 2	Timer 1	Timer 2	Timer 1	Timer 2	Timer 1
	Timer value can change once every 2 states
TIMER _MUX.0 = 1
Time Bus	Timer 4	Timer 3	Timer 2	Timer 1	Timer 4	Timer 3	Timer 2	Timer 1

Timer value can change once every 4 states

A4343-01

Figure 11-3. Sharing the Time Bus

11-8