INTERFACING WITH EXTERNAL MEMORY

15.3.2 Controlling Bus Parameters

For each chip-select output address range, the bus control register BUSCONx (Figure 15-4) determines the wait states, the bus width, and the address/data multiplexing.

The chip-select output signals share package pins with port 3. Use the port registers to configure these pins as general-purpose I/O signals or as chip-select signals (see “Chip-select Signals (EPORT)” on page 7-16. The bus configuration programmed in BUSCON x applies to address range x, regardless of the port 3 pin configurations.

BUSCONx	Address:	1E7CH, 1E84H, 1E8CH
x = 0–2	Reset State:	0003H, 0000H, 0000H

For the address range assigned to chip-select x, the bus control (BUSCONx) register specifies the number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that access address range x.

The chip-select output signals share package pins with port 3. Use the port registers to configure these pins as general-purpose I/O signals or as chip-select signals (see “Chip-select Signals (EPORT)” on page 7-16). The bus configuration programmed in BUSCONx applies to address range x, regardless of the port 3 pin configurations.

7

0

DEMUX

BW16

—

—

—

—

WS1

WS0

Bit

Bit

Function

Number

Mnemonic

7

DEMUX

Address/Data Multiplexing

This bit specifies the address/data multiplexing on AD15:0 for all external

accesses to the address range assigned to chip-select x output.

0 = multiplexed

1 = demultiplexed

6

BW16

Bus Width

This bit specifies the bus width for all external accesses to the address

range assigned to chip-select x output.

0 = 8 bits

1 = 16 bits

5:2

—

Reserved; for compatibility with future devices, write zeros to these bits.

1:0

WS1:0

Wait States

These bits, along with the READY pin, control the number of wait states

for all external accesses to the address range assigned to the chip-select

x channel. Write the desired minimum number of wait states (0–3) to

WS1:0. If READY is low when this number is reached, additional wait

states are added until READY is pulled high.

Figure 15-4. Bus Control (BUSCONx) Registers

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8XC196EA USER’S MANUAL

15.3.3 Chip-select Unit Initial Conditions

A chip reset produces the following initial conditions for the chip-select unit:

•ADDRMSKx = 1FFFH.

•ADDRCOM0 = 1F20H. This asserts CS0# for the 256-byte address range 1F2000– 1F20FFH.

•ADDRCOM1 and ADDRCOM2 = 0000H.

•For the fetch of chip configuration byte 0 (CCB0), BUSCON0 is initialized for an 8-bit bus width, multiplexed mode, and three wait states (DEMUX = 0, BW16 = 0, WS0 = 1, WS1 = 1).

•Before the fetch of chip configuration byte 1 (CCB1), the values of DEMUX, BW16, WS0, and WS1 in BUSCON0 are loaded from CCB0. The external bus is configured according to the new values.

15.3.4 Programming the Chip-select Registers

When programming the chip-select parameters, it is important to avoid a condition in which two chip-selects outputs have overlapping address ranges and different bus-parameter values (wait states, bus width, and multiplexing). Accessing a location in such an overlapping address range can cause unpredictable results.

Use the following sequence to program the chip-select registers after reset:

1.Program chip-select output 0:

1.1.Clear ADDRMSK0.

1.2.Write to ADDRCOM0 to establish the desired base address.

1.3.Write to ADDRMSK0 to establish the desired address range.

1.4.Write the desired bus-parameter values to BUSCON0.

2.While executing in the address range defined in step 1 for chip-select output 0, use the following sequence to program chip-select outputs 1–2. Begin with x = 1.

2.1.Write to ADDRCOMx to establish the desired base address.

2.2.Write to ADDRMSKx to establish the desired address range.

2.3.Write the desired bus-parameter values to BUSCONx.

2.4.Repeat steps 2.1–2.4 for x = 2.

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INTERFACING WITH EXTERNAL MEMORY

15.3.5 Example of a Chip-select Setup

This section shows an example of setting up the chip-select unit and provides details of the chipselect output calculation. This example shows how to set up the chip-select registers for the system shown in Figure 15-5. For each address range, the BUSCONx register (Figure 15-4) specifies the address/data multiplexing (bit 7), the bus width (bit 6), and the number of wait states (bits 0– 1). Table 15-5 lists the characteristics of the three chip-select outputs and shows the corresponding contents of BUSCONx.

Microcontroller			Flash		SRAM
		256K×16			8K×8
CS0#		CE#
CS2#				CE#
A20:0	A18:1	A17:0		A12:0
				A12:0
AD15:0	AD15:0	D15:0		AD7:0
				D7:0
		OE#	WE#	OE#	WE#
RD#
WR#
	A2:0	A2:0	82510
			UART	Rxd
	AD7:0	D7:0		Txd
CS1#		CE#

A3282-01

Figure 15-5. Example System for Setting Up Chip-select Outputs

Table 15-5. BUSCONx Registers for the Example System

	Chip-				Contents of
	select	Multiplexing	Bus Width	Wait States
					BUSCONx
	Output
	CS0#	Demultiplexed	16 bits	0	C0H
	CS1#	Demultiplexed	8 bits	3	83H
	CS2#	Demultiplexed	8 bits	0	80H

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