SERIAL DEBUG UNIT

16.4 CODE RAM ACCESS

Communication to the code RAM through the SDU is accomplished using a limited SSIO format configuration with an additional handshaking operation. (Refer to Table 16-1 on page 16-2 for a description of the four pins required to interface to the SDU.) The SSIO of the SDU module has no master function. It can function only as a slave, allowing communication over a serial link in a bidirectional, single-byte transfer mode. All data transfers must be initiated by the clock source of an external master. Figure 16-5 illustrates a possible interface scheme using an 8XC196Kx SSIO master to control the 8XC196EA SDU slave.

	SC0	CRDCLK
	SD0	CRIN
8XC196Kx		83C196EA
(Master)	SC1	(Slave)
	SD1	CROUT
	Px.x	CRBUSY#

A3304-01

Figure 16-5. SDU Master/Slave Configuration

Figure 16-6 shows the standard 8-bit data-in (DIx) and data-out (DOx) transfer frame. The MSB is sent first, followed by another seven bits before the handshaking is asserted. Handshaking prevents a data underflow or overflow from occurring at the slave. The code RAM busy (CRBUSY#) signal serves this purpose for the slave. The CRBUSY# signal activates automatically one to two state times after the rising edge of the code RAM clock (CRDCLK) edge corresponding to the last data bit of the transmitted 8-bit packet. Each data bit is sampled and latched on the rising edge of CRDCLK.

CRDCLK

CRIN	MSB DI6	DI5	DI4	DI3	DI2	DI1	DI0
CROUT	MSB DO6	DO5	DO4	DO3	DO2	DO1	DO0

CRBUSY#

A3305-01

Figure 16-6. SDU Transmit/Receive Timings

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8XC196EA USER’S MANUAL

16.4.1 Code RAM Data Transfer

The serial transfer of data frames using the SDU must be initiated by an external master device. The structure of a code RAM data transfer must be an eight-bit command byte followed by a specific number of bytes. The command instruction register, SDU_COM, specifies the data length.

Traffic control across the serial link is maintained by the handshaking pin, CRBUSY#. The SDU asserts the CRBUSY# signal to indicate that it is processing a command. The CRBUSY# signal toggles low for a few (three or fewer) states after every eight-bit command and data frame. This allows the state machine time to decode the command and to determine the register destination of a particular byte. (Refer to “Code RAM Data Transfer Example” on page 16-12 for a detailed example of the code RAM message structure.)

16.4.2 Code RAM Access Instructions

Figure 16-7 describes the SDU command byte, and Table 16-3 describes the code RAM access instructions.

SDU_COM

The serial debug unit command byte (SDU_COM) register specifies the instruction, the transfer direction, and the data size (byte or word). The command byte must precede each data frame string in the serial transfer.

7										0
SB	SDU_INT	MS3		MS2		MS1	MS0	W/R#		B/W#
Bit	Bit					Function
Number	Mnemonic
7	SB	Start Bit
		Clear this bit to indicate a valid command byte for synchronization.
6	SDU_INT	SDU Interrupt

This bit is used to generate an interrupt to the CPU.

0 = disable interrupt

1 = enable interrupt

5:2

MS3:0

Mode Select

These bits specify which instruction the SDU will execute. Refer to Table 16-3 for the complete set of instructions.

Figure 16-7. Serial Debug Unit Command Byte (SDU_COM) Register

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SERIAL DEBUG UNIT

SDU_COM

The serial debug unit command byte (SDU_COM) register specifies the instruction, the transfer direction, and the data size (byte or word). The command byte must precede each data frame string in the serial transfer.

7											0
SB	SDU_INT	MS3		MS2			MS1		MS0	W/R#	B/W#
Bit	Bit						Function
Number	Mnemonic
1	W/R#	Write/Read
		This bit specifies the transfer direction.
		0 = read data from code RAM
		1 = write data to code RAM
0	B/W#	Byte/Word

This bit specifies the data transfer size.

0 = word

1 = byte

Figure 16-7. Serial Debug Unit Command Byte (SDU_COM) Register (Continued)

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8XC196EA USER’S MANUAL

					Table 16-3. Code RAM Access Instructions
		Mode Select†			Instruction
	MS3	MS2	MS1	MS0
	0	0	0	0	Reset SDU
					The reset SDU instruction resets all the SDU circuitry and reinitializes all the
					registers to their default value.
					If the SDU was left in an unknown state and your application is attempting to
					re-establish communication with the SDU, the master must send it a
					synchronization sequence. The synchronization sequence consists of six
					consecutive command bytes containing the reset SDU instruction 01111111B
					(7FH). This six-command sequence resynchronizes the SDU, regardless of its
					last state.
					The reset SDU instruction will not reset the microcontroller CPU.
	0	0	0	1	Code RAM Address Access
					The code RAM address access instruction allows access to the code RAM
					address access (CR_ADDR) register. This instruction, in conjunction with the
					16-bit CR_ADDR register, is used to set up the address for the code RAM
					access.
	0	1	0	0	Code RAM Data Access
					The code RAM data access instruction allows access to the code RAM data
					access (CR_DATA) register. This instruction, in conjunction with the 16-bit
					CR_DATA register, is used for data transfers to and from the code RAM.
	0	1	0	1	Breakpoint Address Access
					The breakpoint address access instruction is used to write to the breakpoint
					address access (BP_ADDR) register. This instruction, in conjunction with the
					24-bit BP_ADDR register, is used to specify the address for inserting a
					hardware breakpoint.
	0	1	1	0	Breakpoint Enable
					The breakpoint enable instruction enables immediate breakpoint generation
					when the address on the internal extended memory address bus (EMAB)
					matches the value in BP_ADDR.
					The breakpoint logic (Figure 16-8) includes a comparator that resides on the
					EMAB. If the breakpoint instruction has been programmed, the breakpoint
					logic compares the address on the bus with the address in the BP_ADDR
					register. A match sets an internal flag that exists as a ninth bit in the
					instruction queue. When the flagged instruction is transferred from the
					instruction queue into the instruction register, the CPU executes a TRAP
					instruction and vectors to the TRAP interrupt service routine at FF2010H (see
					“Breakpoint Logic Block Diagram” on page 16-11).
	0	1	1	1	Breakpoint Disable
					The breakpoint disable instruction disables the breakpoint generation.

† All other bit combinations are reserved

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SERIAL DEBUG UNIT

Table 16-3. Code RAM Access Instructions (Continued)

		Mode Select†			Instruction
	MS3	MS2	MS1	MS0
	1	0	1	0	SDU Idle (NOP)
					The idle instruction puts the SDU into an idle state, causing it to wait for
					another instruction without performing any operation. The idle instruction is
					primarily used to write the high byte of data after a word read.
					For example, if during a word read operation a command byte is shifted in, the
					SDU can shift out only eight bits, which is assumed to be the high data byte.
					Eight additional clocks are required to shift out another data frame. To read
					out the next data byte, which is the low data byte, without issuing a new
					command, use the idle instruction.
	1	1	1	1	Reset SDU
					The reset SDU instruction resets all the SDU circuitry and reinitializes all the
					registers to their default value.
					If the SDU was left in an unknown state and your application is attempting to
					re-establish communication with the SDU, the master must send it a
					synchronization sequence. The synchronization sequence consists of six
					consecutive command bytes containing the reset SDU instruction 01111111B
					(7FH). This six-command sequence resynchronizes the SDU, regardless of its
					last state.
					The reset SDU instruction will not reset the microcontroller CPU.

† All other bit combinations are reserved

	BP_ADDR (24)
		1	Instruction Queue (9)
Extended Memory Address Bus (24)	Address Value (24)	Set Break	TRAP
		Logic	MUX
	Comparator	Instruction Register (8)
			A3317-01

Figure 16-8. Breakpoint Logic Block Diagram

16-11