8XC196EA USER’S MANUAL

8.4.4Enabling the Serial Port Interrupts

Each serial port channel has both a transmit interrupt (TIx) and a receive interrupt (RIx). These interrupts indicate completed operations. For mode 0 receptions, the SIO sets the RIx interrupt pending bit after it samples the eighth data bit. For mode 1 and 3 receptions, the SIO sets the RIx interrupt pending bit just before it receives the end of the stop bit. For mode 2 receptions, the SIO sets the RIx interrupt pending bit just before it receives the end of the stop bit only if the ninth data bit received was set. For mode 0 transmissions, the SIO sets the TIx interrupt pending bit immediately after it transmits the eighth data bit, unless a delay is programmed. For mode 1, 2, and 3 transmissions, the SIO sets the TI flag immediately after it starts to transmit the stop bit, unless a delay is programmed. The SIO can delay the setting of the TI flag by one, three, or seven bit times. (See “Programming the Control Register” on page 8-11.)

To enable an interrupt, set the corresponding mask bit in the interrupt mask register (see INT_MASK on page C-33) and execute the EI instruction to globally enable servicing of interrupts. See Chapter 8, “Programming the Control Register,” for more information about interrupts.

8.4.5Determining Serial Port Status

The SPx_STATUS register (Figure 8-8) contains several bits that reflect the status of the serial port. Reading SPx_STATUS clears all bits except TXE and RIP. To check the status of the serial port, copy the contents of the SPx_STATUS register into a shadow register and then execute bittest instructions such as JBC and JBS on the shadow register. Otherwise, the first bit-test instruction will clear the SPx_STATUS register, losing all status information. Since the shadow register is not cleared when read, this method allows you to execute more than one bit-test instruction on the serial port status information. You can also read the interrupt pending register (see INT_PEND on page C-35) to determine the status of the serial port interrupts.

8-16

SERIAL I/O (SIO) PORT

SPx_STATUS	Address:	1F89H, 1F99H
x = 0–1	Reset State:	00H

The serial port status (SPx_STATUS) register contains bits that indicate the status of the serial port x.

7

0

RPE/RB8

RI

TI

FE

TXE

OE

RIP

—

Bit

Bit

Function

Number

Mnemonic

7

RPE/RB8

Received Parity Error/Received Bit 8

For modes 1 and 3, RPE is set if parity is enabled (SPx_CON.2 = 1) and the

data received does not contain the correct parity, as programmed in

SPx_CON.

For mode 2, and for mode 3 with parity disabled, this bit is the ninth data bit

received. (The serial port receive buffer contains the received data bits 0–7.

The received data bit 8 is written to this bit.)

Reading SPx_STATUS clears this bit.

6

RI

Receive Interrupt

This bit indicates whether an incoming data byte has been received.

For modes 0, 1, and 3, this bit is set when the last bit (eighth bit for mode 0,

or stop bit for modes 1 and 3) is sampled. For mode 2, this bit is set when

the stop bit is detected only if the ninth bit received (SPx_STATUS, RB8) is

a one. Reading SPx_STATUS clears this bit.

5

TI

Transmit Interrupt

This bit indicates whether a data byte has finished transmitting.

For mode 0 transmissions, the SIO sets this bit immediately after it

transmits the eighth data bit, unless a delay is selected in the SPx_CON

register. For mode 1, 2, and 3 transmissions, the SIO sets this bit

immediately after it starts to transmit the stop bit, unless a delay is selected

in the SPx_CON register. You can delay setting this bit by one, three, or

seven bit times. Reading SPx_STATUS clears this bit.

4

FE

Framing Error

For modes 1, 2, and 3, this bit is set if the receiver does not detect a valid

stop bit within the appropriate period of time. Reading SPx_STATUS clears

this bit.

For mode 0, this bit has no function.

3

TXE

SBUFx_TX Empty

The SIO sets this bit, along with the TI flag, if the transmit buffer and the

transmit shift register are both empty. Using the SPx_CON register, you can

delay the setting of this bit by one, three, or seven bit times. When set, this

bit indicates that two bytes can be written to the transmit buffer. Writing to

the transmit buffer clears this bit.

Figure 8-8. Serial Port Status (SPx_STATUS) Register

8-17

8XC196EA USER’S MANUAL

SPx_STATUS (Continued)	Address:	1F89H, 1F99H
x = 0–1	Reset State:	00H

The serial port status (SPx_STATUS) register contains bits that indicate the status of the serial port x.

7

0

RPE/RB8

RI

TI

FE

TXE

OE

RIP

—

Bit

Bit

Function

Number

Mnemonic

2

OE

Overrun Error

The SIO sets this bit if data in the receive shift register is loaded into

SBUFx_RX before the previous byte in SBUFx_RX is read. Reading

SPx_STATUS clears this bit.

1

RIP

Reception In Progress

For modes 1, 2, and 3, this bit simplifies detecting an idle data line for

asynchronous, half-duplex operations. A falling edge on RXD (indicating the

possibility of a valid start bit) sets this bit. Either of three conditions clears

this bit:

∙ the start bit is found to be invalid,

∙ the stop bit is received, or

∙ a framing error occurs (there is no valid stop bit within the proper time).

0 = receiver is idle

1 = data is being received

For mode 0, this bit is not useful. A falling edge on RXD sets this bit and a

rising edge clears it.

0

—

Reserved; for compatibility with future devices, write zero to this bit.

Figure 8-8. Serial Port Status (SPx_STATUS) Register (Continued)

8-18

9

Synchronous Serial

I/O (SSIO) Port