CHAPTER 2

ARCHITECTURAL OVERVIEW

The 16-bit 8XC196EA CHMOS microcontroller is designed to handle high-speed calculations and fast input/output (I/O) operations. In addition to its 16-bit external bus, the 8XC196EA has an extended addressing port that provides 5 external address pins, for a total of 21 address pins. With 21 address pins, this microcontroller can access up to 2 Mbytes of linear address space. The 8XC196EA also has a chip-select unit that provides a glueless interface to external memory devices. The extended addressing port and chip-select unit enable the 8XC196EA microcontroller to handle larger, more complex programs and to access more external memory at a faster rate than could earlier MCS® 96 microcontrollers.

2.1TYPICAL APPLICATIONS

MCS 96 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The 8XC196EA is especially well suited to applications that benefit from its processing speed and enhanced peripheral set, such as powertrain control.

2.2MICROCONTROLLER FEATURES

The 8XC196EA is the first member of a new family of MCS 96 microcontrollers incorporating new features for automotive applications such as powertrain control. It has 2 Mbytes of linear address space, providing more space for high-level language compilation than did earlier MCS 96 microcontrollers. It also has three individually programmable chip-select signals and an external bus that can dynamically switch between multiplexed and demultiplexed operation, making it easier to design low-cost memory solutions.

The 8XC196EA has an optional clock multiplier, allowing it to operate at 40 MHz with a less expensive, 20 MHz external clock source. It also has a programmable clock output, allowing you to select one of five output frequencies. The 8XC196EA incorporates a serial debug unit (SDU) that allows read and write access to the internal code/data RAM, aiding in code development and debugging.

In addition to the interrupt controller and peripheral transaction server (PTS), the 8XC196EA incorporates two peripheral interrupt handlers (PIHs). Each PIH handles up to 16 interrupt requests from the event processor array (EPA). With the addition of the PIHs to the interrupt structure, the 8XC196EA can support 44 interrupt sources.

The 8XC196EA has both new and enhanced peripherals. The peripherals that are new to automotive MCS 96 products are a stack overflow module (SOM) and four pulse-width modulators (PWMs) with two channels each. The stack overflow module monitors the stack pointer and causes a nonmaskable interrupt if the stack pointer crosses upper or lower boundaries you define, assisting in code development. Each of the four pulse-width modulators (PWMs) consists of an

2-1

8XC196EA USER’S MANUAL

adjacent pair of PWM channels that can generate two output signals with a fixed, programmable frequency and a variable duty cycle. These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered to produce a smooth analog signal.

The synchronous serial input/output (SSIO) port, event processor array (EPA), and analog-to-dig- ital (A/D) converter have been enhanced for the 8XC196EA.

•The SSIO port provides one bidirectional communication channel or two unidirectional channels. The SSIO is compatible with most protocols because the serial clock is completely configurable. Paired, the SSIO channels can operate in a channel-select mode, allowing for communication in multiple-master systems without additional external hardware.

•The EPA has 4 timer/counters, 17 high-speed capture/compare channels, and 8 output/simulcapture channels. The output/simulcapture channels are output-only channels that simultaneously capture the value of any other timer upon a compare, providing easy conversion between angle and time domains. A pair of timer/counters (timer 1–2 or timer 3–4) can be concatenated to provide a 32-bit timer/counter.

•The A/D converter has sixteen 10-bit channels, a dedicated result register for each channel, and an automatic scan mode that operates without CPU intervention.

Table 2-1 lists the features of the 83C196EA, and Figure 2-1 shows a detailed block diagram.

Table 2-1. Features of the 83C196EA

			Register	Code/Data	I/O Pins	EPA	SIO/	A/D	PWM	Chip-	External
	Pins	ROM	RAM				SSIO			select	Interrupt
				RAM	(Note 2)	Pins		Chnl	Pins
			(Note 1)				Ports			Pins	Pins
	160	8 Kbytes	1 Kbyte	3 Kbytes	132	25	4	16	8	3	1

NOTES:

1.Register RAM amount includes the 24 bytes allocated to core special-function registers (SFRs) and the stack pointer.

2.I/O pins include address, data, and bus control pins and 83 I/O port pins.

Table 2-2 lists the features of the 80C196EA, and Figure 2-2 shows a detailed block diagram.

Table 2-2. Features of the 80C196EA

			Register	Code/Data	I/O Pins	EPA	SIO/	A/D	PWM	Chip-	External
	Pins	ROM	RAM				SSIO			select	Interrupt
				RAM	(Note 2)	Pins		Chnl	Pins
			(Note 1)				Ports			Pins	Pins
	160	None	1 Kbyte	3 Kbytes	132	25	4	16	8	3	1

NOTES:

1.Register RAM amount includes the 24 bytes allocated to core special-function registers (SFRs) and the stack pointer.

2.I/O pins include address, data, and bus control pins and 83 I/O port pins.

2-2

ARCHITECTURAL OVERVIEW

					Port 11	Port 10	EPORT	Port 12
Watchdog	Stack		A/D		Pulse-width	SSIO0
	Overflow
Timer		Converter			Modulators	SSIO1
	Module
Peripheral Addr Bus (10)
Peripheral Data Bus (16)								SIO0	Baud-rate
									Generator
Bus Control					(16)	(24)	Chip-select
								Port 2
					Bus	Bus	Unit
A20:16	Bus
	Controller
					Data	Addr
A15:0								SIO1	Baud-rate
					Memory	Memory	Peripheral		Generator
AD15:0
							Interrupt
							Handler
	Bus-Control						Peripheral	Ports 7,8
	Interface Unit						Transaction
	Queue						Server
									17 Capture/
							Interrupt
									Compares
							Controller
	Microcode
								EPA	4 Timers
	Engine
									8 Output/
	Source (16)								Simulcaptures
	Register							Port 9
				Memory
	RAM
ALU				Interface
	1 Kbyte			Unit
	Destination (16)
						Code/Data	Serial Debug	ROM
						RAM
						3 Kbytes	Unit	8 Kbytes
									A3178-03

Figure 2-1. 83C196EA Detailed Block Diagram

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8XC196EA USER’S MANUAL
					Port 11	Port 10	EPORT	Port 12
Watchdog	Stack		A/D		Pulse-width	SSIO0
	Overflow
Timer		Converter			Modulators	SSIO1
	Module
Peripheral Addr Bus (10)
Peripheral Data Bus (16)								SIO0	Baud-rate
									Generator
Bus Control					(16)	(24)	Chip-select
								Port 2
					Bus	Bus	Unit
A20:16	Bus
	Controller
					Data	Addr
A15:0								SIO1	Baud-rate
					Memory	Memory	Peripheral		Generator
AD15:0
							Interrupt
							Handler
	Bus-Control						Peripheral	Ports 7,8
							Transaction
	Interface Unit
	Queue						Server
									17 Capture/
							Interrupt
									Compares
							Controller
	Microcode
								EPA	4 Timers
	Engine
									8 Output/
	Source (16)								Simulcaptures
	Register							Port 9
				Memory
	RAM
ALU				Interface
	1 Kbyte			Unit
	Destination (16)
						Code/Data
						RAM	Serial Debug
						3 Kbytes		Unit
									A4994-01

Figure 2-2. 80C196EA Detailed Block Diagram

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