CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY

The microcontroller can interface with a variety of external memory devices. Three chip-selects can be individually programmed for bus width, the number of wait states, and a multiplexed or demultiplexed address/data bus. Other features of the external memory interface include ready control for inserting additional wait states, a bus-hold protocol that enables external devices to take control of the bus, and two write-control modes for writing words and bytes to memory. These features provide a great deal of flexibility when interfacing with external memory systems.

In addition to describing the signals and registers related to external memory, this chapter discusses the process of fetching the chip configuration bytes and configuring the external bus. It also provides examples of external memory configurations and chip-select setup.

15.1 INTERNAL AND EXTERNAL ADDRESSES

The address that external devices see is different from the address that the microcontroller generates internally. The microcontroller has 24 address bits internally, but only 21 address pins (A20:0) externally. The absence of the upper three address bits at the external pins causes different internal addresses to have the same external address. For example, the internal addresses FF2080H, 7F2080H, and 1F2080H all appear at the 21 external pins as 1F2080H. The upper three bits of the internal address have no effect on the external address.

The address seen by an external device also depends on the number of address lines that the external system uses. If the address on the external pins (A20:0) is 1F2080H, and only A17:0 are connected to the external device, the external device sees 32080H. The upper five address lines (A20:16) are implemented by the EPORT. Table 15-1 shows how the external address depends on the number of EPORT lines used to address the external device.

Table 15-1. Example of Internal and External Addresses

		Address on the	EPORT Pins	Address Seen by
	Internal Address	Microcontroller	Connected to the
				External Device
		Pins	External Device
			A16	12080H
			A17:16	32080H
	xF2080H
		1F2080H	A18:16	72080H
	(x = 1, 3, 5, 7, 9, B, D, F)
			A19:16	F2080H
			A20:16	1F2080H

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Table 15-1. Example of Internal and External Addresses (Continued)

		Address on the	EPORT Pins	Address Seen by
	Internal Address	Microcontroller	Connected to the
				External Device
		Pins	External Device
			A16	12080H
			A17:16	32080H
	xF2080H
		0F2080H	A18:16	72080H
	(x = 0, 2, 4, 6, 8, A, C, E)
			A19:16	F2080H
			A20:16	0F2080H

15.2 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS

Table 15-2 lists the signals and Table 15-3 lists the registers that are discussed in this chapter. Some of the microcontroller port pins can function as either bus-control signals or general purpose I/O signals. “Using the Special-function Signals” on page 7-11 describes how to configure a port pin as either a general purpose I/O signal or a bus-control signal.

Table 15-2. Bus-control Signals

	Signal	Port Pin	Type	Description
	Name
	A15:0	—	O	System Address Bus
				These address pins provide address bits 0–15 during the entire
				external memory cycle during both multiplexed and demultiplexed bus
				modes.
	A20:16	EPORT.4:0	O	Address Pins 16–20
				These address pins provide address bits 16–20 during the entire
				external memory cycle during both multiplexed and demultiplexed bus
				modes, supporting extended addressing of the 2-Mbyte address
				space.
				NOTE: Internally, there are 24 address bits; however, only 21 exter-
				nal address pins (A20:0) are implemented. The internal
				address space is 16 Mbytes (000000–FFFFFFH) and the
				external address space is 2 Mbytes (000000–1FFFFFH).
				The microcontroller resets to FF2080H in internal memory or
				1F2080H in external memory.
				A20:16 share package pins with EPORT.4:0.

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						INTERFACING WITH EXTERNAL MEMORY
		Table 15-2. Bus-control Signals (Continued)
Signal	Port Pin		Type				Description
Name
AD15:0	P4.7:0		I/O	Address/Data Lines
	P3.7:0			The function of these pins depends on the bus width and mode. When
				a bus access is not occurring, these pins revert to their I/O port
				function.
				16-bit Multiplexed Bus Mode:
				AD15:0 drive address bits 0–15 during the first half of the bus cycle
				and drive or receive data during the second half of the bus cycle.
				8-bit Multiplexed Bus Mode:
				AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0
				drive address bits 0–7 during the first half of the bus cycle and drive or
				receive data during the second half of the bus cycle.
				16-bit Demultiplexed Mode:
				AD15:0 drive or receive data during the entire bus cycle.
				8-bit Demultiplexed Mode:
				AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive
				the data that is currently on the high byte of the internal bus.
ALE	P5.0		O	Address Latch Enable
				This active-high output signal is asserted only during external memory
				cycles. ALE signals the start of an external bus cycle and indicates
				that valid address information is available on the system address/data
				bus (A20:16 and AD15:0 for a multiplexed bus; A20:0 for a
				demultiplexed bus).
				An external latch can use this signal to demultiplex address bits 0–15
				from the address/data bus in multiplexed mode.
				ALE shares a package pin with P5.0.
BHE#	P5.5		O	Byte High Enable†
				During 16-bit bus cycles, this active-low output signal is asserted for
				word and high-byte reads and writes to external memory. BHE#
				indicates that valid data is being transferred over the upper half of the
				system data bus. Use BHE#, in conjunction with address bit 0 (A0 for
				a demultiplexed address bus, AD0 for a multiplexed address/data
				bus), to determine which memory byte is being transferred over the
				system bus:
				BHE#		AD0 or A0	Byte(s) Accessed
				0		0	both bytes
				0		1	high byte only
				1		0	low byte only
				BHE# shares a package pin with P5.5 and WRH#.
				†	When this pin is configured as a special-function signal
					(P5_MODE.5 = 1), the chip configuration register 0 (CCR0)
					determines whether it functions as BHE# or WRH#. CCR0.2 = 1
					selects BHE#; CCR0.2 = 0 selects WRH#.

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Table 15-2. Bus-control Signals (Continued)

	Signal	Port Pin	Type	Description
	Name
	BREQ#	P5.4	O	Bus Request
				This active-low output signal is asserted during a hold cycle when the
				bus controller has a pending external memory cycle. When the bus-
				hold protocol is enabled (WSR.7 is set), the P5.4/BREQ# pin can
				function only as BREQ#, regardless of the configuration selected
				through the port configuration registers (P5_MODE, P5_DIR, and
				P5_REG). An attempt to change the pin configuration is ignored until
				the bus-hold protocol is disabled (WSR.7 is cleared).
				The microcontroller can assert BREQ# at the same time as or after it
				asserts HLDA#. Once it is asserted, BREQ# remains asserted until
				HOLD# is deasserted.
				BREQ# shares a package pin with P5.4 and TMODE#.
	CLKOUT	P2.7	O	Clock Output
				Output of the internal clock generator. You can select one of five
				frequencies: f, f/2, f/4, f/8, or f/16. CLKOUT has a 50% duty cycle.
				CLKOUT shares a package pin with P2.7
	CS2:0#	EPORT.7:5	O	Chip-select Lines 0–2
				The active-low output CSx# is asserted during an external memory
				cycle when the address to be accessed is in the range programmed
				for chip select x. If the external memory address is outside the range
				assigned to the three chip selects, no chip-select output is asserted
				and the bus configuration defaults to the CS2# values.
				Immediately following reset, CS0# is automatically assigned to the
				range FF2000–FF20FFH (1F2000–1F20FFH if external).
				CS2:0# share package pins with EPORT.7:5.
	EA#	—	I	External Access
				This input determines whether memory accesses to the upper 7
				Kbytes of ROM (FF2400–FF3FFFH) are directed to internal or
				external memory. These accesses are directed to internal memory if
				EA# is held high and to external memory if EA# is held low. For an
				access to any other memory location, the value of EA# is irrelevant.
				EA# is sampled and latched only on the rising edge of RESET#.
				Changing the level of EA# after reset has no effect.
	HLDA#	P2.6	O	Bus Hold Acknowledge
				This active-low output indicates that the CPU has released the bus as
				the result of an external device asserting HOLD#. When the bus-hold
				protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can function
				only as HLDA#, regardless of the configuration selected through the
				port configuration registers (P2_MODE, P2_DIR, and P2_REG). An
				attempt to change the pin configuration is ignored until the bus-hold
				protocol is disabled (WSR.7 is cleared).
				HLDA# shares a package pin with P2.6 and ONCE#.

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				INTERFACING WITH EXTERNAL MEMORY
		Table 15-2. Bus-control Signals (Continued)
Signal	Port Pin		Type	Description
Name
HOLD#	P2.5		I	Bus Hold Request
				An external device uses this active-low input signal to request control
				of the bus. When the bus-hold protocol is enabled (WSR.7 is set), the
				P2.5/HOLD# pin can function only as HOLD#, regardless of the
				configuration selected through the port configuration registers
				(P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin
				configuration is ignored until the bus-hold protocol is disabled (WSR.7
				is cleared).
				HOLD# shares a package pin with P2.5.
INST	P5.1		O	Instruction Fetch
				When high, INST indicates that an instruction is being fetched from
				external memory. The signal remains high during the entire bus cycle
				of an external instruction fetch. INST is low for data accesses,
				including interrupt vector fetches and chip configuration byte reads.
				INST is low during internal memory fetches.
				INST shares a package pin with P5.1.
RD#	P5.3		O	Read
				Read-signal output to external memory. RD# is asserted only during
				external memory reads.
				RD# shares a package pin with P5.3.
READY	P5.6		I	Ready Input
				This active-high input can be used to insert wait states in addition to
				those programmed in the chip configuration byte 0 (CCB0) and the
				bus control x register (BUSCONx). CCB0 is programmed with the
				minimum number of wait states (0–3) for an external fetch of CCB1,
				and BUSCONx is programmed with the minimum number of wait
				states (0–3) for all external accesses to the address range assigned to
				the chip-select x channel. If READY is low when the programmed
				number of wait states is reached, additional wait states are added until
				READY is pulled high.
				READY shares a package pin with P5.6.
WR#	P5.2		O	Write†
				This active-low output indicates that an external write is occurring.
				This signal is asserted only during external memory writes.
				WR# shares a package pin with P5.2 and WRL#.
				† When this pin is configured as a special-function signal
				(P5_MODE.2 = 1), the chip configuration register 0 (CCR0)
				determines whether it functions as WR# or WRL#. CCR0.2 = 1
				selects WR#; CCR0.2 = 0 selects WRL#.

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Table 15-2. Bus-control Signals (Continued)

	Signal	Port Pin	Type	Description
	Name
	WRH#	P5.5	O	Write High†
				During 16-bit bus cycles, this active-low output signal is asserted for
				high-byte writes and word writes to external memory. During 8-bit bus
				cycles, WRH# is asserted for all write operations.
				WRH# shares a package pin with P5.5 and BHE#.
				† When this pin is configured as a special-function signal
				(P5_MODE.5 = 1), the chip configuration register 0 (CCR0)
				determines whether it functions as BHE# or WRH#. CCR0.2 = 1
				selects BHE#; CCR0.2 = 0 selects WRH#.
	WRL#	P5.2	O	Write Low†
				During 16-bit bus cycles, this active-low output signal is asserted for
				low-byte writes and word writes to external memory. During 8-bit bus
				cycles, WRL# is asserted for all write operations.
				WRL# shares a package pin with P5.2 and WR#.
				† When this pin is configured as a special-function signal
				(P5_MODE.2 = 1), the chip configuration register 0 (CCR0)
				determines whether it functions as WR# or WRL#. CCR0.2 = 1
				selects WR#; CCR0.2 = 0 selects WRL#.

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			INTERFACING WITH EXTERNAL MEMORY
		Table 15-3. External Memory Interface Registers
	Register	Address	Description
	Mnemonic
	ADDRCOM0	1E78H	Address Compare
	ADDRCOM1	1E80H	Holds address bits 8–20 of the base address of the address range assigned
	ADDRCOM2	1E88H
			to CSx#.
	ADDRMSK0	1E7AH	Address Mask
	ADDRMSK1	1E82H	Determines the size of the address range (256 bytes–2 Mbyte) assigned to
	ADDRMSK2	1E8AH
			CSx#.
	BUSCON0	1E7CH	Bus Control
	BUSCON1	1E84H	Determines the bus configuration for external accesses to the address range
	BUSCON2	1E8CH
			assigned to CSx#. The bus parameters are 8- or 16-bit bus width,
			multiplexed or demultiplexed address/data lines, and the number of wait
			states inserted into each bus cycle.
	CCR0	†	Chip Configuration 0
			Enables or disables the IDLPD #1 and IDLPD #2 instructions. When
			enabled, the IDLPD #1 instruction causes the microcontroller to enter idle
			mode and the IDLPD #2 instruction causes the microcontroller to enter
			powerdown mode. This register also selects the write-control mode and
			contains the bus-control parameters for fetching chip configuration byte 1.
	CCR1	†	Chip Configuration 1
			Selects the 64-Kbyte or 2-Mbyte addressing mode and controls whether the
			internal ROM is mapped only into page FFH or into both pages FFH and
			00H.
	EP_DIR	1FE3H	Extended Port Direction
			In I/O mode, each bit of the extended port I/O direction (EP_DIR) register
			controls the configuration of the corresponding pin. Clearing a bit configures
			a pin as a complementary signal; setting a bit configures a pin as an open-
			drain signal.
			Any pin that is configured for its extended-address function is forced to the
			complementary output mode except during reset, hold, idle, and powerdown.
	EP_MODE	1FE1H	Extended Port Mode
			The EPORT pins 0–4 can function as general-purpose I/O signals or as
			extended address signals. EPORT pins 5–7 can function as general-purpose
			I/O signals or as chip-select signals.
			Each bit of the extended port mode (EP_MODE) register controls whether
			the corresponding pin functions as a general-purpose I/O signal or as an
			extended-address signal. Setting a bit configures a pin as an extended-
			address signal; clearing a bit configures a pin as a general-purpose I/O
			signal.
	EP_PIN	1FE7H	Extended Port Input
			Each bit of the extended port input (EP_PIN) register reflects the current
			state of the corresponding pin, regardless of the pin configuration.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1).

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Table 15-3. External Memory Interface Registers (Continued)

	Register	Address	Description
	Mnemonic
	EP_REG	1FE5H	Extended Port Data Output
			The EPORT pins 0–4 can function as general purpose I/O signals or as
			extended address signals. EPORT pins 5–7 can function as general purpose
			I/O signals or as chip-select signals.
			For I/O Mode (EP_MODE.x = 0)
			When a port pin is configured as a complementary output (EP_DIR.x =
			0), setting the corresponding EP_REG bit drives a one on the pin and
			clearing the corresponding EP_REG bit drives a zero on the pin.
			When a port pin is configured as a high impedance input or an open-drain
			output (EP_DIR.x = 1), clearing the corresponding EP_REG bit drives a
			zero on the pin and setting the corresponding EP_REG bit floats the pin,
			making it available as a high impedance input.
			For Special-function Mode (EP_MODE.x = 1)
			When an EPORT pin is configured as a special-function signal (either a
			chip-select or an extended-address signal), the EP_REG bit value is
			immaterial because the address bus or the chip-select unit controls the
			pin.
	P2_DIR	1FD2H	Port Direction Register
	P5_DIR	1FF3H	Each bit controls the configuration of the corresponding pin. Clearing a bit
			configures a pin as a complementary output; setting a bit configures a pin as
			a high-impedance input or an open-drain output.
	P2_MODE	1FD0H	Port Mode Register
	P5_MODE	1FF1H	Each bit controls the mode of the corresponding pin. Setting a bit configures
			a pin as a special-function signal; clearing a bit configures a pin as a general-
			purpose I/O signal.
	P2_PIN	1FD6H	Port Pin Register
	P5_PIN	1FF7H	Each bit reflects the current state of the corresponding pin, regardless of the
			pin’s mode and configuration.
	P2_REG	1FD4H	Port Data Output Register
	P5_REG	1FF5H	For I/O Mode (Px_MODE.x = 0)
			When a port pin is configured as a complementary output (Px_DIR.x = 0),
			setting the corresponding port data bit drives a one on the pin, and
			clearing the corresponding port data bit drives a zero on the pin.
			When a port pin is configured as a high-impedance input or an open-
			drain output (Px_DIR.x = 1), clearing the corresponding port data bit
			drives a zero on the pin, and setting the corresponding port data bit floats
			the pin, making it available as a high-impedance input.
			For Special-function Mode (Px_MODE.x = 1)
			When a port pin is configured as an output (either complementary or
			open-drain), the corresponding port data bit value is immaterial because
			the corresponding on-chip peripheral or system function controls the pin.
			To configure a pin as a high-impedance input, set both the Px_DIR and
			Px_REG bits.

†The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after reset. The CCBs reside at addresses FF2018H (CCB0) and FF201AH (CCB1).

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