MINIMUM HARDWARE CONSIDERATIONS

13.6 RESETTING THE MICROCONTROLLER

Reset forces the microcontroller into a known state. As soon as RESET# is asserted, the I/O pins, the control pins, and the registers are driven to their reset states. Table B-5 on page B-15 lists the reset states of the pins. See Table C-2 on page C-2 for the reset values of the SFRs. The microcontroller remains in its reset state until RESET# is deasserted. When RESET# is deasserted, the bus controller fetches the chip configuration bytes (CCBs), loads them into the chip configuration registers (CCRs), and then fetches the first instruction. Figure 13-7 shows the reset-sequence timing.

RESET#

Pin

Internal

Reset

CLKOUT

ALE

	(Note 1)
RD#	t
CS0#

CS2:1#

t

A15:0			2018H	201AH
				CCB1
AD7:0	00H	18H	CCB0	1AH
				(Note 2)
AD15:8	00H		20H Strongly Driven	20H Strong. Drv.
A20:16				0FH Strongly Driven

Bus parameters defined by CCB0 (bus width, multiplexed or demultiplexed mode, number of wait states) take effect here (at start of second bus cycle). BUSCON0 is changed here by value of CCB0.

Notes:

1.Depends on number of wait states defined in CCB0.

2.If bus is multiplexed, AD15:8 strongly drive 20H.

2. If bus is demultiplexed, AD15:8 drive the data that is currently on the high byte of the internal bus.

A3385-01

Figure 13-7. Reset Timing Sequence

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8XC196EA USER’S MANUAL

The following events will reset the microcontroller (see Figure 13-8):

•an external device pulls the RESET# pin low

•the CPU executes a reset (RST) instruction

•the CPU executes an idle/powerdown (IDLPD) instruction with an illegal key operand

•the watchdog timer (WDT) overflows

•the clock failure detection (CFD) logic is enabled and a clock failure occurs

The following paragraphs describe each of these reset methods in more detail.

		Internal	External
	Reset State	VCC
		Clock
Internal	Machine	RRST†
Reset	Trigger
Signal
	Stop
		~200 Ω	RESET#
	CLR
	Q	Q1

SET

RST Instruction

WDT Overflow

IDLPD Invalid Key

CFD Occurrence

† See the datasheet for minimum and maximum RRST values.

A3384-01

Figure 13-8. Internal Reset Circuitry

13.6.1 Generating an External Reset

To reset the device, hold the RESET# pin low for at least one state time after the power supply is within tolerance and the oscillator has stabilized. When RESET# is first asserted, the device turns on a pull-down transistor (Q1 in Figure 13-8) for 16 state times. This enables the RESET# signal to function as the system reset.

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MINIMUM HARDWARE CONSIDERATIONS

The simplest way to reset the microcontroller is to insert a capacitor between the RESET# pin and VSS, as shown in Figure 13-9. The microcontroller has an internal pull-up resistor (RRST), as shown in Figure 13-8. RESET# should remain asserted for at least one state time after VCC and XTAL1 have stabilized and met the operating conditions specified in the datasheet. A capacitor of 4.7 µF or greater should provide sufficient reset time, as long as V CC rises quickly.

					RESET#
+
				4.7 μF	MCS® 96
					Microcontroller

A6027-01

Figure 13-9. Minimum Reset Circuit

Other devices in the system may not be reset because the capacitor will keep the voltage above VIL. Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system-reset pulse. Figure 13-10 shows an example of a system-reset circuit. In this example, D2 creates a wired-OR gate connection to the reset pin. An internal reset, system power-up, or SW1 closing will generate the system-reset signal.

		Vcc
	(1)		Vcc
			(2)
	D1	R
			D2
			4.7 kΩ

SW1	C	Schmitt Triggers
		System reset signal
		to external circuitry

Notes:

1.D1 provides a faster cycle time for repetitive power-on resets.

2.Optional pull-up for faster recovery.

RESET#

MCS® 96

Microcontroller

A6032-01

Figure 13-10. Example of a System Reset Circuit

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8XC196EA USER’S MANUAL

13.6.2 Issuing the Reset (RST) Instruction

The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times. It also clears the processor status word (PSW), sets the master program counter (PC) to FF2080H, and resets the special function registers (SFRs). See Table 13-10 on page 13-11 for the reset values of the SFRs.

13.6.3 Issuing an Illegal IDLPD Key Operand

The device resets itself if an illegal key operand is used with the idle/powerdown (IDLPD) command. The legal keys are “1” for idle mode and “2” for powerdown mode. Any key greater than “3” will cause the device to execute a reset sequence. (See Appendix A for a description of the IDLPD command.)

13.6.4 Enabling the Watchdog Timer

The watchdog timer (WDT) is a 16-bit counter that resets the microcontroller when the counter overflows (every 64K state times). The WDE bit (bit 3) of CCR1 controls whether the watchdog is enabled immediately or is disabled until the first time it is cleared. If the WDE bit in CCR1 is clear, the watchdog is immediately activated. Software must clear the watchdog timer register to avoid a reset. If the WDE bit in CCR1 is set, the watchdog is disabled until the first time you clear it.

You must write two consecutive bytes to the watchdog register (location 0AH) to clear it. For the 83C196EA, the first byte must be 1EH; however, the second byte determines the reset interval and can be one of four values (Table 13-2). Only the values listed in the table are valid; an invalid value will not clear the register, so the counter will overflow and the watchdog will reset the device. It is recommended that you disable interrupts before writing to the watchdog register. If an interrupt occurs between the two writes, the watchdog register will not be cleared.

Table 13-2. Selecting the Watchdog Reset Interval

First Byte	Second Byte	Reset Interval
1EH	E1H	64K states
1EH	A1H	128K states (2 × 64K)
1EH	61H	256K states (4 × 64K)
1EH	21H	512K states (8 × 64K)

If enabled, the watchdog continues to run in idle mode. The device must be awakened before the end of the reset interval to clear the watchdog; otherwise, the watchdog will reset the microcontroller, which causes it to exit idle mode.

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