STANDARD AND PTS INTERRUPTS
Table 6-2. Interrupt and PTS Control and Status Registers (Continued)
Mnemonic	Address	Description
PIH0_PTSSRV	1E94H	Peripheral Interrupt Handler (PIH) PTS Service Registers
PIH1_PTSSRV	1EA4H	The bits in these registers are set by hardware to request an end-
		of-PTS interrupt.
PIH0_VEC_BASE	1E92H	Peripheral Interrupt Handler (PIH) Vector Base Address Registers
PIH1_VEC_BASE	1EA2H	These registers contain bits 6–15 of the PIH interrupt vector
		address.
		Always initialize PIH0_VEC_BASE to 20C0H and
		PIH1_VEC_BASE to 2100H.
PIH0_VEC_IDX	1E90H	Peripheral Interrupt Handler Vector Index Address Registers
PIH1_VEC_IDX	1EA0H	These registers contain the number of the highest priority, active,
		standard PIH interrupt request.
PSW	No direct access	Processor Status Word
		This register contains one bit that globally enables or disables
		servicing of all maskable interrupts and another that enables or
		disables the PTS. These bits are set or cleared by executing the
		enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS),
		and disable PTS (DPTS) instructions.
PTSSEL	0004H, 0005H	PTS Select Register
		This register selects either a PTS interrupt service request or a
		standard interrupt service request for each of the maskable
		interrupt requests.
		Never use this register to disable PTS service for individual PIH
		interrupts. Instead, either use the PIHx_PTSSEL register to
		disable PTS service for individual PIH interrupt sources or use the
		INT_MASK registers to mask the PIHx_PTS or PIHx_INT
		interrupts.
PTSSRV	0006H, 0007H	PTS Service Register
		The bits in this register are set by hardware to request an end-of-
		PTS interrupt.

6.3INTERRUPT SOURCES, PRIORITIES, AND VECTOR ADDRESSES

Table 6-3 lists the interrupt sources, their default priorities (30 is highest and 0 is lowest), and their vector addresses. Higher priority interrupts are serviced before lower priority interrupts. A low-priority interrupt is always interrupted by a higher priority interrupt, but not by another interrupt of equal or lower priority. The absolute highest priority interrupt is not interrupted by any other interrupt source.

The unimplemented opcode and software trap interrupts are not prioritized; they go directly to the interrupt controller for servicing. The priority resolver determines the priority of all other pending interrupt requests. NMI and the stack overflow error have higher priority than any other prioritized interrupts. PTS interrupts always have higher priority than standard interrupts. The priority resolver selects the highest priority pending request and the interrupt controller selects the corresponding vector location in special-purpose memory. This vector contains the starting (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine. PTSCBs

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8XC196EA USER’S MANUAL

must be located on a quad-word boundary in the internal register file. Interrupt service routines must begin execution in page FFH, but can jump anywhere after the initial vector is taken.

Table 6-3. Interrupt Sources, Vectors, and Priorities

		Interrupt Controller					PTS Service
			Service
Interrupt Source	Mnemonic
					†					Priority
		Name	Vector		Priority		Name	Vector
Nonmaskable Interrupt	NMI	INT15	FF203EH		30		—	—		—
Stack Overflow Error	Stack	INT14	FF203CH		14		—	—		—
PIH0 PTS Interrupt	PIH0_PTS	INT13	Table 6-4		13		PTS13	Table 6-4		28
PIH0 Standard Interrupt	PIH0_INT	INT12	Table 6-4		12		PTS12	Table 6-4		27
PIH1 PTS Interrupt	PIH1_PTS	INT11	Table 6-5		11		PTS11	Table 6-5		26
PIH1 Standard Interrupt	PIH1_INT	INT10	Table 6-5		10		PTS10	Table 6-5		25
SSIO Channel 1 Transfer	SSIO1	INT09	FF2032H		9		PTS09	FF2052H		24
SSIO Channel 0 Transfer	SSIO0	INT08	FF2030H		8		PTS08	FF2050H		23
Dummy PTS Cycle	—	—	—	—		—	FF2016H		—
Dummy Standard Interrupt	—	—	FF2014H		—	—		—	—
Unimplemented Opcode	—	—	FF2012H		—	—		—	—
Software TRAP Instruction	—	—	FF2010H		—	—		—	—
Serial Debug Unit Interrupt	SDU	INT07	FF200EH		7		PTS07	FF204EH		22
EXTINT Pin	EXTINT	INT06	FF200CH		6		PTS06	FF204CH		21
SIO1 Receive	RI1	INT05	FF200AH		5		PTS05	FF204AH		20
SIO1 Transmit	TI1	INT04	FF2008H		4		PTS04	FF2048H		19
A/D Conversion Complete	AD_DONE	INT03	FF2006H		3		PTS03	FF2046H		18
EPA Channel 3–16 Overrun	EPAx_OVR	INT02	FF2004H		2		PTS02	FF2044H		17
SIO0 Receive	RI0	INT01	FF2002H		1		PTS01	FF2042H		16
SIO0 Transmit	TI0	INT00	FF2000H		0		PTS00	FF2040H		15

† The higher the priority number, the higher the priority.

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