CHAPTER 16

SERIAL DEBUG UNIT

The serial debug unit (SDU) is a new design for the MCS® 96 microcontroller architecture. This new peripheral allows you to read and write the contents of the code RAM using a high-speed dedicated serial link.

The SDU peripheral has four objectives:

•to provide a real-time method for developing and debugging code with no CPU overhead

•to provide a simple user interface to the device without requiring extensive external hardware

•to support reading and writing of all internal and external memory during interrogation mode

•to support breakpoints in both internal and external memory development systems

This chapter explains and illustrates how to transfer data to and from the code RAM. Examples using the SDU command instruction set and the reduced instruction set monitor (RISM) routine are provided for clarification.

16.1 SERIAL DEBUG UNIT (SDU) FUNCTIONAL OVERVIEW

The SDU (Figure 16-1) is a simple four-pin interface peripheral. It is similar to, and can communicate with, other synchronous serial I/O (SSIO) devices. It allows the code RAM to function as a dual-port RAM. This is because it can read from and write to the code RAM across a serial link, without CPU overhead.

	CRDCLK		SDU	Code RAM
	CRIN	Slave SSIO		Access Block	Code
			State Machine
	CROUT	Interface	and	Breakpoint	RAM
		Block	Register Block		(3 Kbytes)
	CRBUSY#			Logic Block
				CodeAddressRAM(16)Bus	CodeRAMData(16)Bus
					A3358-01

Figure 16-1. SDU Block Diagram

16-1

8XC196EA USER’S MANUAL

The SDU module consists of four main functional blocks:

•the slave SSIO interface block, which controls communication to and from the SDU

•the SDU state machine and register block, which decodes the SDU instruction set and contains the data registers

•the code RAM access block, which permits the SDU to read or write the code RAM without CPU intervention

•the breakpoint logic block, which permits the insertion of hardware breakpoints during the code RAM interrogation

16.2 SDU SIGNALS AND REGISTERS

Table 16-1 describes the SDU signals and Table 16-2 describes the control register.

			Table 16-1. SDU Signals
	SDU	SDU	Description
	Signal(s)	Signal Type
	CRBUSY#	O	Code RAM Busy
			When active, this signal indicates the SDU is busy processing a code RAM
			command. No data can be transferred during this time.
	CRDCLK	I	Code RAM Data Clock
			Provides the clock signal for the SDU. The maximum clock frequency is
			one-half the operating frequency (f/2).
	CRIN	I	Code RAM Data Input
			Serial input for test instructions and data into the SDU. Data is transferred
			eight bits at a time with the most-significant bit (MSB) first. Each bit is
			sampled and latched on the rising edge of CRDCLK.
	CROUT	O	Code RAM Data Output
			Serial output for data from the SDU. Data is transferred eight bits at a time
			with the MSB first. Each data bit changes one CPU state time after the
			rising edge of CRDCLK.

	Table 16-2. SDU Control Register
Mnemonic	Description
SDU_COM	SDU Command Register
	This byte register determines the instruction the SDU will execute, the data
	direction, and the size (byte or word) of the transaction. It can also force an interrupt
	to the CPU for accessing the RISM.

16-2