INTERFACING WITH EXTERNAL MEMORY

15.5.4 Comparison of Multiplexed and Demultiplexed Buses

In a multiplexed system, where AD15:0 carry both address and data, bus activities are time-com- pressed in comparison with a demultiplexed system, where the address and data have separate pins (A20:0 and AD15:0). The compression is reflected in differences in specifications for the demultiplexed and multiplexed bus. The demultiplexed bus can accommodate slower memory devices than a multiplexed bus can. (Consult the datasheet for specifications.)

15.6 WAIT STATES (READY CONTROL)

An external device can use the READY input to lengthen an external bus cycle. When an external address is placed on the bus, the external device can pull the READY signal low to indicate it is not ready. In response, the microcontroller inserts wait states to lengthen the bus cycle until the external device asserts the READY signal. Each wait state adds one CLKOUT period to the bus cycle. The CLKOUT period is as programmed in the CLKOUT_CON register (see “External Timing” on page 2-12). The following figures assume the CLKOUT period is twice the internal oscillator period (2t).

The READY signal is effective for all bus cycles, including the CCB0 fetch (which has three internal wait states). Bits WS0 and WS1 in CCB0 specify the wait states for the CCB1 fetch. Thereafter, the WS1:0 bits in the BUSCONx registers control the wait states, and the READY signal can be used to insert additional wait states. (See “Controlling Bus Parameters” on page 15-13.)

The external device must meet setup and hold timings when using the READY signal to insert wait states into a bus cycle (see Figures 15-13 and 15-14 and Table 15-7). Because a decoded, valid address is used to generate the READY signal, the setup time is specified relative to the address being valid. This specification, TAVYV, indicates how much time the external device has to decode the address and assert READY after the address is valid.

The external device must hold READY low until the minimum TCLYX timing specification is met. Typically, this is a minimum of 0 ns from the time CLKOUT goes low. Do not exceed the maximum TCLYX specification or additional (unwanted) wait states might be added. Refer to the datasheets for the current TAVYV and TCLYX specifications.

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	8XC196EA USER’S MANUAL
			TCLYX (max)
	CLKOUT
	TAVYV	TCLYX (min)
	READY
			TLHLH + 2t
	ALE
			TRLRH + 2t
	RD#		TRLDV + 2t
	AD15:0		TAVDV + 2t
		Address Out	Data In
	(read)
			TWLWH + 2t
	WR#
	AD15:0		TQVWH + 2t
		Address Out	Data Out
	(write)
	BHE#, INST
	A20:16	Extended Address Out
	CSx#
			A3249-01

Figure 15-13. READY Timing Diagram — Multiplexed Mode

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INTERFACING WITH EXTERNAL MEMORY

	CLKOUT	TCLYX (max)
	TAVYV	TCLYX (min)
	READY
		TLHLH + 2t
	ALE
		TRLRH + 2t
	RD#	TRLDV + 2t
	AD15:0	TAVDV + 2t
	(read)	Data In
		TWLWH + 2t
	WR#
	AD15:0	TQVWH + 2t
		Data Out
	(write)
	BHE#, INST
	A20:0	Address Out
	CSx#
		A3259-02

Figure 15-14. READY Timing Diagram — Demultiplexed Mode

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8XC196EA USER’S MANUAL

	Table 15-7. READY Signal Timing Definitions
Symbol	Definition
TAVDV	Address Valid to Input Data Valid
	Maximum time the memory device has to output valid data after the microcontroller outputs a
	valid address.
TAVYV	Address Valid to READY Setup
	Maximum time the external device has to pull READY low after the microcontroller outputs the
	address to guarantee that at least one wait state will occur.
T	READY Hold after CLKOUT† High
CHYX
	If maximum specification is exceeded, additional wait states may occur.
T	READY Hold after CLKOUT† Low
CLYX
	Minimum time the level of the READY signal must be valid after CLKOUT falls.
TLHLH	ALE Cycle Time
	Minimum time between ALE pulses.
TQVWH	Data Valid to WR# High
	Time between data being valid on the bus and the microcontroller deasserting WR#.
TRLDV	RD# Low to Input Data Valid
	Maximum time the memory system has to output valid data after the microcontroller asserts
	RD#.
TRLRH	RD# Low to RD# High
	RD# pulse width.
TWLWH	WR# Low to WR# High
	WR# pulse width.

† Assumes CLKOUT is equal to twice the internal operating period (2t).

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