PULSE-WIDTH MODULATOR
	PWMx_y_PERIOD		Address:	See Table 10-2 on page 10-5
	x = 0, 2, 4, 6		Reset State:	00H
	y = 1, 3, 5, 7
	The PWM period (PWMx_y_PERIOD) register of each module controls the period of the two PWM
	outputs. Write a value to this register to specify the number of state counts necessary for decre-
	menting the PWM counter. The value of PWMx_y_PERIOD is loaded into the PWM period count
	register whenever the count equals zero.
	7			0
			PWM Period
	Bit		Function
	Number
	7:0	PWM Period
		This register controls the period of the PWM outputs. The value of PWMx_y_PERIOD is
		loaded into the PWMx_y_COUNT register whenever the count equals zero.

Figure 10-3. PWM Period (PWMx_y_PERIOD) Register

10.5 PROGRAMMING THE DUTY CYCLE

The values written to the PWM_CONTROL and PWMx_y_PERIOD registers control the width of the high pulse, effectively controlling the duty cycle. The eight-bit value written to the control register is loaded into a buffer, and this value is used during the next period. Use the following duty cycle formula to calculate a desired duty cycle for a given value of PWM_CONTROL, and then write the value to the appropriate register.

	Duty Cycle (in %)	=	PWM-----------------_---CONTROL------------------------------- × 100
			256
	Pulse width (in µs)	=	Duty Cycle × TPWM
			-------------------100----------------------------

where:

PWM_CONTROL	=	eight-bit decimal value to load into the PWM_CONTROL register
TPWM	=	output period on the PWM pin, in μs

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8XC196EA USER’S MANUAL

PWMx_CONTROL, PWMy_CONTROL	Address:	See Figure 10-2 on page 10-5
x = 0, 2, 4, 6	Reset:	00H
y = 1, 3, 5, 7

The PWM control (PWMx_CONTROL, PWMy_CONTROL) registers determine the duty cycle of the PWM channel pair. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle). Variables x and y represent the evenand odd-numbered members of an adjacent PWM channel pair, respectively.

7

0

PWM Duty Cycle

Bit

Function

Number

	7:0	PWM Duty Cycle
		This register controls the PWM duty cycle. A zero loaded into this register causes the
		PWM to output a low continuously (0% duty cycle). An FFH in this register causes the
		PWM to have its maximum duty cycle (99.6% duty cycle).
		Figure 10-4. PWM Control (PWMx_CONTROL, PWMy_CONTROL) Registers

10.5.1 Sample Calculations

For the purpose of our example, assume the following initial conditions:

•FXTAL1 = 16 MHz

•PWM_CONTROL = 8AH (138 decimal)

•PWMx_y_PERIOD = 4FH (79 decimal)

Using the equation on page 10-5 to calculate the desired period of the PWM output waveform, we find that:

•If the PLL circuitry is enabled, the pulsewidth is held high for 0.69 ms of the total 1.28 ms period, resulting in a duty cycle of approximately 54%.

•If the PLL circuitry is disabled, the same initial values produce a period of 2.56 ms and a pulsewidth of 1.38 ms. This also results in a duty cycle of approximately 54%.

10.5.2 Reading the Current Value of the Down-counter

You can read the PWMx_y_COUNT register (Figure 10-5) to find the current value of the period counter.

10-8

				PULSE-WIDTH MODULATOR
	PWMx_y_COUNT		Address:	See Table 10-2 on page 10-3
	x = 0, 2, 4, 6		Reset State:	00H
	y = 1, 3, 5, 7
	(read only)
	The PWM count (PWMx_y_COUNT) register provides the current value of the period counter.
	7			0
			PWM Count Value
	Bit Number		Function
	7:0	PWM Count Value
		This register contains the current value of the period counter.

Figure 10-5. PWM Count (PWMx_y_COUNT) Register

10.5.3 Enabling the PWM Outputs

Each PWM output shares a pin with a port, so you must configure it as a special-function output signal before using the PWM function. To do so, follow this sequence:

1.Clear the corresponding bit of P11_DIR (see Table 10-4).

2.Set the corresponding bit of P11_MODE (see Table 10-4).

3.Set or clear the corresponding bit of P11_REG (see Table 10-4).

Table 10-4 shows the alternate port function along with the register setting that selects the PWM output instead of the port function.

Table 10-4. PWM Output Alternate Functions

PWM Output	Alternate Port Function	PWM Output Enabled When
PWM0	P11.0	P11_DIR.0 = 0, P11_MODE.0 = 1, P11_REG = X
PWM1	P11.1	P11_DIR.1 = 0, P11_MODE.1 = 1, P11_REG = X
PWM2	P11.2	P11_DIR.2 = 0, P11_MODE.2 = 1, P11_REG = X
PWM3	P11.3	P11_DIR.3 = 0, P11_MODE.3 = 1, P11_REG = X
PWM4	P11.4	P11_DIR.4 = 0, P11_MODE.4 = 1, P11_REG = X
PWM5	P11.5	P11_DIR.5 = 0, P11_MODE.5 = 1, P11_REG = X
PWM6	P11.6	P11_DIR.6 = 0, P11_MODE.6 = 1, P11_REG = X
PWM7	P11.7	P11_DIR.7 = 0, P11_MODE.7 = 1, P11_REG = X

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8XC196EA USER’S MANUAL

10.5.4 Generating Analog Outputs

PWM modules can generate a rectangular pulse train that varies in duty cycle and period. Filtering this output will create a smooth analog signal. To make a signal swing over the desired analog range, first buffer the signal and then filter it with either a simple RC network or an active filter. Figure 10-6 is a block diagram of the type of circuit needed to create the smooth analog signal.

MCS®96	Buffer	Filter	Power
Microcontroller	to Make	(Passive	Amp
	Output Swing	or		Analog
PWM	Rail	Active)	(Optional)	Output
	to
	Rail	(Optional)
				A2391-02

Figure 10-6. D/A Buffer Block Diagram

Figure 10-7 shows a sample circuit used for low output currents (less than 100 μA). Consider temperature and power-supply drift when selecting components for the external D/A circuitry. With proper components, a highly accurate 8-bit D/A converter can be made using the PWM.

PWM
		R				-			Analog
MCS®96					+				Output
	74ACxxx			C	Op Amp
Microcontroller
	Buffer

Consider both ripple and response time requirements when selecting R and C.

A2390-02

Figure 10-7. PWM to Analog Conversion Circuitry

10-10

11

Event Processor

Array (EPA)