I/O PORTS

7.2CONFIGURING THE PORT PINS

Each port 2, 5, 7–12 and EPORT pin can be configured independently to operate as a specialfunction signal or an I/O signal. In addition, these signals can be independently configured to operate as complementary outputs, high-impedance inputs, or open-drain outputs. Unlike the other ports, the pins of ports 3 and 4 are not individually configurable. Ports 3 and 4 can be configured as complementary or open-drain ports. The remainder of this section details how to configure the port pins.

7.2.1Configuring Ports 2, 5, 7–12, and EPORT

Using the port mode register, you can individually configure each pin for port 2, 5, 7–12, and EPORT to operate either as a general-purpose I/O signal (I/O mode) or as a special-function signal (special-function mode). In either mode, three configurations are possible: complementary output, high-impedance input, or open-drain output. The port direction and data output registers select the configuration for each pin. Complementary output means that the microcontroller drives the signal high or low. High-impedance input means that the microcontroller floats the signal. Open-drain output means that the microcontroller drives the signal low or floats it. For I/O mode, the port data output register determines whether the microcontroller drives the signal high, drives it low, or floats it. For special-function mode, the on-chip peripheral or system function determines whether the microcontroller drives the signal high or low for complementary outputs.

The pins for ports 2, 5, 7–12, and EPORT are weakly pulled high during and after reset. Initializing the pins by writing to the port mode register turns off the weak pull-ups. To ensure that the ports are initialized correctly, follow this suggested initialization sequence:

1.Write to Px_DIR (or EP_DIR) to configure the individual pins. Clearing a bit configures a pin as a complementary output. Setting a bit configures a pin as a high-impedance input or open-drain output.

2.Write to Px_MODE (or EP_MODE) to select either I/O or special-function mode. Writing to Px_MODE (regardless of the value written) turns off the weak pull-ups. Even if the entire port is to be used as I/O (its default configuration after reset), you must write to Px_MODE (or EP_MODE) to ensure that the weak pull-ups are turned off.

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3.Write to Px_REG (or EP_REG).

For complementary output configurations:

In I/O mode, write the data that is to be driven by the pins to the corresponding Px_REG (or EP_REG) bits. In special-function mode, the value is immaterial because the on-chip peripheral or system function controls the pin. However, you must still write to Px_REG (or EP_REG) to initialize the pin.

For high-impedance input or open-drain output configurations:

In I/O mode, write to Px_REG (or EP_REG) to either float the pin, making it available as a high impedance input, or pull it low. Setting the corresponding Px_REG (or EP_REG) bit floats the pin; clearing the corresponding Px_REG (or EP_REG) bit pulls the pin low. In special-function mode, if the on-chip peripheral uses the pin as an input signal, you must set the corresponding Px_REG (or EP_REG) bit so that the pin can be driven externally. If the on-chip peripheral uses the pin as an output signal, the value of the corresponding Px_REG (or EP_REG) bit is immaterial because the on-chip peripheral or system function controls the pin. However, you must still write to Px_REG (or EP_REG) to initialize the pin.

Table 7-4 lists the control register values for each possible configuration.

Table 7-4. Control Register Values for Each Configuration

Desired Pin Configuration	Configuration Register Settings
General-purpose I/O Signal	Px_DIR	Px_MODE	Px_REG
Complementary, driving 0	0	0	0
Complementary, driving 1	0	0	1
Open drain, strongly driving 0	1	0	0
Input (high impedance)	1	0	1
Special-function Signal	Px_DIR	Px_MODE	Px_REG
Complementary, output value controlled by peripheral	0	1	X
Open drain, output value controlled by peripheral	1	1	X
Input (high impedance)	1	1	1

7.2.2Configuring Ports 3 and 4 (Address/Data Bus)

The microcontroller has two bus modes available: multiplexed and demultiplexed. For multiplexed mode, during external memory bus cycles, ports 3 and 4 serve as the lower 16 address bits and the data bus. For demultiplexed mode, during external memory bus cycles, ports 3 and 4 serve only as the data bus. When boot code resides in internal memory (EA# inactive), port 3 and 4 pins can function as general-purpose I/O pins when an external memory cycle is not required. When boot code resides in external memory (EA# active), port 3 and 4 pins should not be used for gen- eral-purpose I/O unless external logic can differentiate bus cycles from general-purpose I/O.

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I/O PORTS

Ports 3 and 4 are eight-bit, memory-mapped I/O ports. These ports contain three control registers (P34_DRV, P3_REG, and P4_REG) and two status registers (P3_PIN and P4_PIN). The port registers are addressable only with indirect or indexed addressing — they cannot be windowed.

During external memory bus cycles, the processor takes control of ports 3 and 4 and automatically configures them as complementary outputs for driving address and/or data or as inputs for reading data. For general-purpose I/O, two configurations are possible: complementary and open drain. The P34_DRV register selects the configuration for each port. With a complementary configuration, the microcontroller drives the signal high or low. With an open-drain configuration, the microcontroller drives the signal low or floats it.

To configure a port for general-purpose I/O, first select a complementary or open-drain configuration by writing to P34_DRV. Set P34_DRV.7 to configure port 3 as complementary; clear P34_DRV.7 to configure port 3 as open-drain. Likewise, set P34_DRV.6 to configure port 4 as complementary; clear P34_DRV.6 to configure port 4 as open-drain. In complementary mode, write the output data to the corresponding Px_REG bit. In open-drain mode, set the corresponding Px_REG bit to float a pin or clear the corresponding bit to pull it low. When the device requires access to external memory, it takes control of the port and drives the address or data onto the pins. The address or data bits replace your output during this time. When the external access is completed, the device restores your data onto the pins.

To use the port pins as inputs, first clear the corresponding P34_DRV bit to configure the port as open-drain. Next, set the corresponding Px_REG bit to drive the pin to a high-impedance state. You may then read the pin’s input value in the P x_PIN register. When the device requires access to external memory, it automatically takes control of the port; therefore, you must configure the input source to avoid contention on the bus.

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7.2.3Port Configuration Example

Assume that you wish to configure the pins of port 7 as shown in Table 7-5.

Table 7-5. Port 7 Configuration Example

Port Pin(s)	Configuration	Data
P7.0, P7.1	high-impedance input	high impedance
P7.2, P7.3	open-drain, driving 0	0
P7.4	open-drain, output with external pull-up	1 (because of external pull-up)
P7.5, P7.6	complementary, driving 0	0
P7.7	complementary, driving 1	1

To do so, you could use the following example code segment. shows the state of each pin after reset and after execution of each line of the example code.

LDB P7_DIR,#00011111B

LDB P7_MODE,#00000000B

LDB P7_REG,#10010011B

Table 7-6. Port 7 Pin States After Reset and After Example Code Execution

	Action or Code			Resulting Pin States†
		P7.7	P7.6	P7.5	P7.4	P7.3	P7.2	P7.1	P7.0
	Reset	WK	WK	WK	WK	WK	WK	WK	WK
	LDB P7_DIR, #00011111B	1	1	1	WK	WK	WK	WK	WK
	LDB P7_MODE, #00000000B	1	1	1	HZ	HZ	HZ	HZ	HZ
	LDB P7_REG, #10010011B	1	0	0	1††	0	0	HZ	HZ

†WK = weakly pulled high, HZ = high impedance.

††Pulled high by external pull-up.

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