INTERFACING WITH EXTERNAL MEMORY

15.3 THE CHIP-SELECT UNIT

The chip-select unit provides three outputs, CS2:0#, for selecting an external device during an external bus cycle. During an external memory access, a chip-select output CSx# is asserted if the address falls within the address range assigned to that chip-select. The bus width, the number of wait states, and multiplexed or demultiplexed address/data lines are programmed independently for each of the three chip-selects. If the external address is outside the range of the three chipselects, the chip-select 2 bus control register determines the wait states, bus width, and multiplexing for the current bus cycle, and no chip-select is asserted.

Figure 15-1 illustrates the microcontroller’s calculation of a chip-select output CSx# for a given external memory address. Address bits 8–20 of the memory address are compared (XORed) bitwise with the 13 least-significant bits (BASE20:8) of the ADDRCOMx register. If all of the bits match, CSx# is asserted. Additionally, if some bits do not match, CSx# is still asserted if, for each non-matching bit in ADDRCOMx, the corresponding bit in ADDRMSKx is cleared. The 13 leastsignificant bits are named MASK20:8 for their function in masking bits BASE20:8.

Address			ADDRCOMx		ADDRMSKx
20	8 7	0	15	13 12	0 15	13 12	0
				BASE20:8		MASK20:8
bit 20				bit 12		bit 12

CSx#

20	8 7	0	15	13 12	0 15	13 12	0
				BASE20:8		MASK20:8
	bit 8			bit 0		bit 0

A3281-01

Figure 15-1. Calculation of a Chip-select Output

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8XC196EA USER’S MANUAL

15.3.1 Defining Chip-select Address Ranges

This section describes the ADDRCOMx and ADDRMSKx registers and how to set them up for a desired address range. The ADDRCOMx register (Figure 15-2) and ADDRMSKx register (Figure 15-3) control the assertion of each chip-select output. The BASE20:8 bits in the ADDRCOMx register determine the base address of the address range. The MASK20:8 bits in the ADDRMSKx register determine the size of the address range.

ADDRCOMx	Address:	1E78H, 1E80H, 1E88H
x = 0–2	Reset State:	1F20H, 0000H, 0000H

The address compare (ADDRCOMx) register specifies the base (lowest) address of the address range. The base address of a 2n-byte address range must be on a 2n-byte boundary.

15										8
—	—			—	BASE20		BASE19	BASE18	BASE17	BASE16
7										0
BASE15	BASE14		BASE13		BASE12		BASE11	BASE10	BASE9	BASE8
Bit	Bit						Function
Number	Mnemonic
15:13	—			Reserved; for compatibility with future devices, write zeros to these bits.
12:0	BASE20:8			Base Address Bits
				Write address bits 20–8 of the base address of the address range
				assigned to chip-select x to these bits.

Figure 15-2. Address Compare (ADDRCOMx) Registers

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INTERFACING WITH EXTERNAL MEMORY

ADDRMSKx	Address:	1E7AH, 1E82H, 1E8AH
x = 0–2	Reset State:	1FFFH

The address mask (ADDRMSKx) register, together with the address compare register, defines the address range that is assigned to the chip-select x output, CSx#. The address mask register determines the size of the address range, which must be 2n bytes, where n = 8, 9, . . , 21. For a 2n-byte address range, calculate n1 = 21– n, and set the n1 most-significant bits of MASK20:8 in the address mask register.

15											8
—	—			—	MASK20		MASK19	MASK18	MASK17		MASK16
7											0
MASK15	MASK14		MASK13		MASK12		MASK11	MASK10	MASK9		MASK8
Bit	Bit						Function
Number	Mnemonic
15:13	—			Reserved; for compatibility with future devices, write zeros to these bits.
12:0	MASK20:8			Address Mask Bits
				For a 2n-byte address range, set the n1 most-significant bits of
				MASK20:8, where n1 = 21 – n.

Figure 15-3. Address Mask (ADDRMSKx) Registers

Observe the following restrictions in choosing an address range for a chip-select output:

•The addresses in the address range must be contiguous.

•The size of the address range must be 2n bytes, where n = 8, 9, ..., 21. This corresponds to block sizes of 256 bytes, 512 bytes, ..., 2 Mbyte.

•The base address of a 2n-byte address range must be on a 2n-byte boundary (that is, the base address must be evenly divisible by 2n). For example, the base address of a 256-Kbyte range must be 00000H, 40000H, 80000H, or C0000H. Table 15-4 shows the base addresses for some address-range sizes.

•The address ranges for different chip-selects must not overlap, unless their BUSCONx parameters (wait states, bus width, and multiplexing) have the same values. If BUSCONx registers have different parameter values and an address in their overlapping region is accessed, the results are unpredictable. See “Example of a Chip-select Setup” on page 15-15 for a chip-select initialization procedure that avoids this difficulty.

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Table 15-4. Base Addresses for Several Sizes of the Address Range

Address-	2 Mbyte	1 Mbyte	512 Kbyte	256 Kbyte		512 bytes	256 bytes
Range Size	(221)	(220)	(219)	(218)		(29)	(28)
				1C0000H		1FFE00H	1FFF00H
				180000H		1FFC00H	1FFE00H
				140000H		1FFA00H	1FFD00H
Base				100000H	• • •	• • •	• • •
Addresses			180000H	0C0000H		000600H	000300H
			100000H	080000H		000400H	000200H
		100000H	080000H	040000H		000200H	000100H
	000000H	000000H	000000H	000000H		000000H	000000H

For an address range satisfying these restrictions, set up the ADDRCOMx and ADDRMSKx registers as follows:

•Place address bits 20–8 of the base address into bits BASE20:8 in the ADDRCOM x register (Figure 15-2).

•For an address range of 2n bytes, set the n1 most-significant bits of MASK20:8 in the ADDRMSKx register (Figure 15-3), where n1 = 21 – n.

For example, assume that chip-select output x is to be assigned to a 32-Kbyte address range with base address 1E0000H. The address range size is 32 × 1024 = 215, and n1 = 21 –15 = 6. To set up the registers, write address bits 20–8 of 1E0000H to BASE20:8 in the ADDRCOM x register, and set the 6 most-significant bits of MASK20:8 in the ADDRMSKx register:

ADDRCOMx = 1EF00H

ADDRMSKx = 1F80H

Note that the 32-Kbyte address range could not have 4000H as base address, for example, because 4000H is not on a 32-Kbyte boundary.

“Example of a Chip-select Setup” on page 15-15 shows another example of setting up the chipselect unit.

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