8XC196EA USER’S MANUAL

Table 4-4. 8XC196EA Peripheral SFRs (Continued)

Chip-select 0 and A/D Converter SFRs

Address	High (Odd) Byte	Low (Even) Byte
1E7EH	Reserved for Intel	Reserved for Intel
1E7CH	Reserved	BUSCON0
1E7AH	ADDRMSK0 (H)	ADDRMSK0 (L)
1E78H	ADDRCOM0 (H)	ADDRCOM0 (L)
1E76H	AD_TIME	AD_TEST0
1E74H	Reserved for Intel	AD_COMMAND
1E72H	AD_RESULT (H)	AD_RESULT (L)
1E70H	AD_SCAN (H)	AD_SCAN (L)
1E6EH	AD_RESULT15 (H)	AD_RESULT15 (L)
1E6CH	AD_RESULT14 (H)	AD_RESULT 14 (L)
1E6AH	AD_RESULT13 (H)	AD_RESULT13 (L)
1E68H	AD_RESULT12 (H)	AD_RESULT12 (L)

†Must be addressed as a word.

Chip-select 0 and A/D Converter SFRs (Cont’d)

	Addres	High (Odd) Byte	Low (Even) Byte
	s
	1E66H	AD_RESULT11 (H)	AD_RESULT11 (L)
	1E64H	AD_RESULT10 (H)	AD_RESULT10 (L)
	1E62H	AD_RESULT9 (H)	AD_RESULT9 (L)
	1E60H	AD_RESULT8 (H)	AD_RESULT8 (L)
	1E5EH	AD_RESULT7 (H)	AD_RESULT7 (L)
	1E5CH	AD_RESULT6 (H)	AD_RESULT6 (L)
	1E5AH	AD_RESULT5 (H)	AD_RESULT5 (L)
	1E58H	AD_RESULT4 (H)	AD_RESULT4 (L)
	1E56H	AD_RESULT3 (H)	AD_RESULT3 (L)
	1E54H	AD_RESULT2 (H)	AD_RESULT2 (L)
	1E52H	AD_RESULT1 (H)	AD_RESULT1 (L)
	1E50H	AD_RESULT0 (H)	AD_RESULT0 (L)

4.2.5Register File

The register file is divided into an upper register file and a lower register file (Figure 4-4). The upper register file consists of general-purpose register RAM. The lower register file contains additional general-purpose register RAM along with the stack pointer (SP) and the CPU specialfunction registers (SFRs).

Table 4-5 on page 4-15 lists the register file memory addresses. The RALU accesses the lower register file directly, without the use of the memory controller. It also accesses a windowed location directly (see “Windowing” on page 4-17). Only the upper register file and the peripheral SFRs can be windowed. Registers in the lower register file and registers being windowed can be accessed with direct addressing.

NOTE

The register file must not contain code. An attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory.

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MEMORY PARTITIONS

Page 00H	Address
	03FFH

General-purpose

Register RAM

	Address			0100H
	03FFH		General-purpose	00FFH
		Upper
	0100H	Register File	Register RAM	001AH
	00FFH		Stack Pointer	0019H
		Lower		0018H
		Register File	CPU SFRs	0017H
	0000H			0000H
				A0301-02

Figure 4-4. Register File Memory Map

Table 4-5. Register File Memory Addresses

	Address	Description	Addressing Modes
	Range
	03FFH	General-purpose register RAM; upper register file	Indirect, indexed, extended,
	0100H		windowed direct
	00FFH	General-purpose register RAM; lower register file	Direct, indirect, indexed, extended
	001AH
	0019H	Stack pointer (SP); lower register file	Direct
	0018H
	0017H	CPU special-function registers (SFRs); lower register file	Direct
	0000H

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8XC196EA USER’S MANUAL

4.2.5.1General-purpose Register RAM

The lower register file contains general-purpose register RAM. The stack pointer locations can also be used as general-purpose register RAM when stack operations are not being performed. The RALU can access this memory directly, using direct addressing.

The upper register file also contains general-purpose register RAM. The RALU normally uses indirect or indexed addressing to access the RAM in the upper register file. Windowing enables the RALU to use direct addressing to access this memory, providing fast context switching of interrupt tasks and faster program execution. (Refer to Chapter 3, “Programming Considerations,” for a discussion of addressing modes, and see “Windowing” on page 4-17 for details on windowing.) PTS control blocks and the stack are most efficient when located in the internal code RAM or in the upper register file.

4.2.5.2Stack Pointer (SP)

Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address of the stack. The SP must point to a word (even) address that is two bytes (for 64-Kbyte mode) or four bytes (for 2-Mbyte mode) greater than the desired starting address. Before the CPU executes a subroutine call or interrupt service routine, it decrements the SP (by two in 64-Kbyte mode; by four in 2-Mbyte mode). Next, it copies (PUSHes) the address of the next instruction from the program counter onto the stack. It then loads the address of the subroutine or interrupt service routine into the program counter. When it executes the return-from-subroutine (RET) instruction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the contents of the top of the stack (that is, the return address) into the program counter. Finally, it increments the SP (by two in 64-Kbyte mode; by four in 2-Mbyte mode).

Subroutines may be nested. That is, each subroutine may call others. The CPU PUSHes the contents of the program counter onto the stack each time it executes a subroutine call. The stack grows downward as entries are added. The only limit to the nesting depth is the amount of available memory. As the CPU returns from each nested subroutine, it POPs the address off the top of the stack, and the next return address moves to the top of the stack.

Your program must load a word-aligned (even) address into the stack pointer. Select an address that is two bytes (for 64-Kbyte mode) or four bytes (for 2-Mbyte mode) greater than the desired starting address because the CPU automatically decrements the stack pointer before it pushes the first byte of the return address onto the stack. Remember that the stack grows downward, so allow sufficient room for the maximum number of stack entries. The stack must be located in page 00H, in either the internal register file, the internal code RAM, or external RAM. The stack can be used most efficiently when it is located in the upper register file or internal code RAM.

The following example initializes the top of the upper register file as the stack.

LD

SP, #400H

;Stack begins at 03FEH and grows downward

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