8XC196EA USER’S MANUAL

13.2 APPLYING AND REMOVING POWER

When power is first applied to the microcontroller, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; otherwise, operation might be unpredictable. Similarly, when powering down a system, RESET# should be brought low before VCC is removed; otherwise, an inadvertent write to an external location might occur. Carefully evaluate the possible effect of power-up and power-down sequences on a system.

13.3 NOISE PROTECTION TIPS

The fast rise and fall times of high-speed CMOS logic often produce noise spikes on the power supply lines and outputs. To minimize noise, it is important to follow good design and board layout techniques. We recommend liberal use of decoupling capacitors and transient absorbers. Add 0.01 µF bypass capacitors between V CC and each VSS pin and a 1.0 µF capacitor between V REF and ANGND to reduce noise (Figure 13-2). Place the capacitors as close to the device as possible. Use the shortest possible path to connect VSS lines to ground and to each other.

VCC

+5 V

VREF

+

MCS®

96

+

VREF

Microcontroller

1.0

F

SS

SS

SS

ANGND

V

V

V

*

Analog

*

Digital

Ground

*

Ground

Plane

Plane

5 V

Return

Power Source

* Use 0.01 F bypass capacitors for maximum decoupling.

A6026-01

Figure 13-2. Power and Return Connections

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MINIMUM HARDWARE CONSIDERATIONS

If the A/D converter will be used, connect VREF to a separate reference supply to minimize noise during A/D conversions. Even if the A/D converter will not be used, VREF and ANGND must be connected. Refer to “Analog Ground and Reference Voltages” on page 12-16 for a detailed discussion of A/D power and ground recommendations.

Multilayer printed circuit boards with separate V CC and ground planes also help to minimize noise. For more information on noise protection, refer to AP-125, Designing Microcontroller Systems for Noisy Environments (order number 210313) and AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications (order number 272637).

13.4 THE ON-CHIP OSCILLATOR CIRCUITRY

The on-chip oscillator circuit (Figure 13-3) consists of a crystal-controlled, positive reactance oscillator. In this application, the crystal operates in a parallel resonance mode. The feedback resistor (Rf) consists of paralleled n-channel and p-channel FETs controlled by the internal powerdown signal. In powerdown mode, Rf acts as an open and the output drivers are disabled, which disables the oscillator. Both the XTAL1 and XTAL2 pins have built-in electrostatic discharge (ESD) protection.

NOTE

Although the maximum external clock input frequency is 40MHz, the maximum oscillator input frequency is limited to 20MHz.

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8XC196EA USER’S MANUAL

To internal
circuitry	VCC

XTAL1	Rf	XTAL2
		(Output)
(Input)

Oscillator Enable# (from powerdown circuitry)

VSS

A6041-01

Figure 13-3. On-chip Oscillator Circuit

Figure 13-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended operating temperatures, and crystal specifications. Consult the manufacturer’s datasheet for performance specifications and required capacitor values. With high-quality components, 20 pF load capacitors (CL) are usually adequate for frequencies above 1 MHz.

Noise spikes on the XTAL1 or XTAL2 pin can cause a miscount in the internal clock-generating circuitry. Capacitive coupling between the crystal oscillator and traces carrying fast-rising digital signals can introduce noise spikes. To reduce this coupling, mount the crystal oscillator and capacitors near the device and use short, direct traces to connect to XTAL1, XTAL2, and VSS. To further reduce the effects of noise, use grounded guard rings around the oscillator circuitry and ground the metallic crystal case.

13-6

MINIMUM HARDWARE CONSIDERATIONS

C1

XTAL1

MCS® 96

Microcontroller

XTAL2

C2

Quartz Crystal

Note:

Mount the crystal and capacitors close to the device using short, direct traces to XTAL1, XTAL2, and Vss. When using a crystal, C1=C2»20 pF. When using a ceramic resonator, consult the manufacturer for recommended oscillator circuitry.

A6028-01

Figure 13-4. External Crystal Connections

In cost-sensitive applications, you may choose to use a ceramic resonator instead of a crystal oscillator. Ceramic resonators may require slightly different load capacitor values and circuit configurations. Consult the manufacturer’s datasheet for the requirements.

13.5 USING AN EXTERNAL CLOCK SOURCE

To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure 13-5). To ensure proper operation, the external clock source must meet the minimum high and

low times (TXHXX and TXLXX) and the maximum rise and fall transition times (TXLXH and TXHXL) illustrated in Figure 13-6. The longer the rise and fall times, the higher the probability that exter-

nal noise will affect the clock generator circuitry and cause unreliable operation. See the datasheet for required XTAL1 voltage drive levels and actual specifications.

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8XC196EA USER’S MANUAL

			Vcc
External					4.7 kΩ*
							XTAL1
Clock Input
							MCS® 96
	Clock Driver
							Microcontroller
		No Connection					XTAL2

* Required if TTL driver is used. Not needed if CMOS driver is used.

A6029-01

Figure 13-5. External Clock Connections

TXHXX		TXLXH		TXHXL
0.7 VCC + 0.5 V	TXLXX		0.7 VCC + 0.5 V
XTAL1	0.3 VCC	0.5 V	0.3 VCC	0.5 V
			TXLXL
				A6030-01

Figure 13-6. External Clock Drive Waveforms

At power-on, the interaction between the internal amplifier and its feedback capacitance (i.e., the Miller effect) may cause a load of up to 100 pF at the XTAL1 pin if the signal at XTAL1 is weak (such as might be the case during start-up of the external oscillator). This situation will go away when the XTAL1 input signal meets the VIL and VIH specifications (listed in the datasheet). If these specifications are met, the XTAL1 pin capacitance will not exceed 20 pF.

13-8