ARCHITECTURAL OVERVIEW

2.5INTERNAL PERIPHERALS

The internal peripheral modules provide special functions for a variety of applications. This section provides a brief description of the peripherals; subsequent chapters describe them in detail.

2.5.1I/O Ports

The 8XC196EA has 11 input/output ports, ports 2–5, ports 7–12, and the EPORT. In general, you can configure individual port pins to serve as standard I/O or to carry special-function signals associated with on-chip peripherals or off-chip components. Ports 3 and 4 are exceptions; they are controlled at the port level, not at the pin level. When the bus controller needs to use the external bus, it takes control of the ports. When the external bus is idle, you can use the ports for I/O.

Ports 2, 7, 8, 9, and 11 are eight-bit, bidirectional, standard ports. Port 10 is a six-bit, bidirectional standard port. The standard ports share pins with individually selectable special-function signals. The standard ports can be windowed and accessed with direct addressing.

Ports 3 and 4 are eight-bit, bidirectional, memory-mapped ports that share pins with the multiplexed address/data bus. The EPORT is an eight-bit, bidirectional, memory-mapped port; it shares five of its pins with the five upper address lines, A20:16, to support extended addressing. Port 5 is an eight-bit, bidirectional, memory-mapped port that shares pins with individually selectable control signals. Port 12 is a five-bit, bidirectional, memory-mapped port; it shares three of its pins with signals that enable test-ROM execution. Memory-mapped ports must be accessed using indirect, indexed, or extended addressing; they cannot be windowed. See Chapter 7, “I/O Ports,” for more information.

2.5.2Serial I/O (SIO) Port

The 8XC196EA has a two-channel serial I/O port. The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchronous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous modes are full duplex, meaning that they have dedicated receive and transmit data signals. The receiver is buffered, so the reception of a second byte can begin before the first byte is read. The transmitter is also buffered, allowing continuous transmissions. The SIO port has two channels (channels 0 and 1) with identical signals and registers. See Chapter 8, “Serial I/O (SIO) Port,” for details.

2.5.3Synchronous Serial I/O (SSIO) Port

The synchronous serial I/O (SSIO) port provides for simultaneous, bidirectional communications between two MCS 96 family microcontrollers or between an MCS 96 microcontroller and another synchronous serial I/O device. The SSIO port consists of two identical transceiver channels with a dedicated baud-rate generator.

The SSIO port provides one bidirectional communication channel or two unidirectional channels. The SSIO is compatible with most protocols because the serial clock is completely configurable. Paired, the SSIO channels can operate in a channel-select mode, allowing for communication in multiple-master systems without additional external hardware. See Chapter 9, “Synchronous Serial I/O (SSIO) Port,” for more information.

2-15

8XC196EA USER’S MANUAL

2.5.4Event Processor Array (EPA) and Timer/Counters

The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it. This is a capture event. In the output mode, the EPA monitors a timer until its value matches that of a stored time value. When a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin. This is a compare event. Both capture and compare events can initiate interrupts, which can be serviced by either the interrupt controller or the PTS.

The 8XC196EA has an enhanced EPA with 4 timer/counters, 17 capture/compare channels, and 8 specialized compare-only channels. A compare-only channel can capture the value of any timer other than its reference timer at the time of a compare event. Capturing the timer value while simultaneously triggering the compare event output is called output/simulcapture. This feature simplifies conversion between angle and time domains.

Timers 1–4 are 16-bit up/down timer/counters that can be clocked internally or externally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clocked externally. Each pair of timer/counters (timers 1–2 and timers 3–4) can be concatenated to provide two 32bit timer/counters. See Chapter 11, “Event Processor Array (EPA),”for additional information on the EPA and timer/counters.

2.5.5Analog-to-digital Converter

The analog-to-digital (A/D) converter converts an analog input voltage to a digital equivalent. Resolution is either 8 or 10 bits; sample and convert times are programmable. Conversions can be performed on the analog ground and reference voltage, and the results can be used to calculate gain and zero-offset errors. The internal zero-offset compensation circuit enables automatic zerooffset adjustment. The A/D also has a threshold-detection mode that can generate an interrupt when a programmable threshold voltage is crossed in either direction. The 8XC196EA’s enhanced A/D converter has an automatic scan mode that operates without CPU intervention. In addition, it has a dedicated result register for each analog input channel. See Chapter 12, “Analog- to-digital (A/D) Converter,” for more information.

2.5.6Pulse-width Modulator (PWM)

The output waveform from each PWM channel is a variable duty-cycle pulse with a programmable frequency. Several types of motors require a PWM waveform for most efficient operation. When filtered, the PWM waveform produces a DC level that can change in 256 steps by varying the duty cycle. The number of steps per PWM period is also programmable (8 bits). See Chapter 10, “Pulse-width Modulator,” for more information.

2.5.7Stack Overflow Module

The stack overflow module monitors the stack pointer (SP) and causes a monmaskable interrupt if the stack pointer crosses upper or lower boundaries you define, assisting in code development. See Chapter 5, “Stack Overflow Module,” for details.

2-16