8XC196EA USER’S MANUAL

PIH1_PTSSRV	Address:	1EA4H
	Reset State:	0000H

The PTS service (PIH1_PTSSRV) register for peripheral interrupt handler 1 is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PIH1_PTSSEL bit and sets the PIH1_PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PIH1_PTSSRV bit. The end-of-PTS interrupt service routine must set the PIH1_PTSSEL bit to reenable the PTS channel.

15

EPA16	OS7	OS6	OS5
7
OS0	OVRTM1	OVRTM2	OVRTM3

8

OS4	OS3	OS2	OS1
			0
OVRTM4	OVR0	OVR1	OVR2

Bit

Function

Number

15:0 A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt through its standard interrupt vector.

The standard interrupt vector locations are as follows:

Bit Mnemonic	Interrupt	Standard Vector
EPA16	EPA Capture/Compare Channel 16	FF213CH
OS7	Output Simulcapture Channel 7	FF2138H
OS6	Output Simulcapture Channel 6	FF2134H
OS5	Output Simulcapture Channel 5	FF2130H
OS4	Output Simulcapture Channel 4	FF212CH
OS3	Output Simulcapture Channel 3	FF2128H
OS2	Output Simulcapture Channel 2	FF2124H
OS1	Output Simulcapture Channel 1	FF2120H
OS0	Output Simulcapture Channel 0	FF211CH
OVRTM1	Timer 1 Overflow/Underflow	FF2118H
OVRTM2	Timer 2 Overflow/Underflow	FF2114H
OVRTM3	Timer 3 Overflow/Underflow	FF2110H
OVRTM4	Timer 4 Overflow/Underflow	FF210CH
OVR0	EPA Channel 0 Capture Overrun	FF2108H
OVR1	EPA Channel 1 Capture Overrun	FF2104H
OVR2	EPA Channel 2 Capture Overrun	FF2100H

Figure 6-22. PIH1 PTS Service (PIH1_PTSSRV) Register

6.6.2Selecting the PTS Mode

The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTS mode (Figure 6-23). The function of bits 0–4 differ for each PTS mode. Refer to the sections that describe each mode in detail to see the function of these bits. Table 6-6 on page 6-18 lists the cycle execution times for each PTS mode.

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STANDARD AND PTS INTERRUPTS

PTSCON											Address: PTSCB + 1
The PTS control (PTSCON) register selects the PTS mode and sets up control functions for that
mode.
7													0
M2	M1		M0			†			†	†		†	†
Bit	Bit								Function
Number	Mnemonic
7:5	M2:0		PTS Mode
			These bits select the PTS mode:
			M2	M1		M0
			0	0		0	dummy mode
			0	0		1	block transfer
			0	1		0	reserved
			0	1		1	reserved
			1	0		0	reserved
			1	0		1	single transfer
			1	1		0	missed-event
			1	1		1	reserved

† The function of this bit depends upon which mode is selected. See the PTS control block description in each PTS mode section.

Figure 6-23. PTS Mode Selection Bits (PTSCON Bits 7:5)

6.6.3Single Transfer Mode

In single transfer mode, an interrupt causes the PTS to transfer a single byte or word (selected by the BW bit in PTSCON) from one memory location to another. This mode is typically used with serial I/O or synchronous serial I/O interrupts. It can also be used with the EPA to move captured time values from the event-time register to internal RAM for further processing. See AP-445, 8XC196KR Peripherals: A User’s Point of View , for application examples with code. Figure 6-24 shows the PTS control block for single transfer mode.

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8XC196EA USER’S MANUAL

PTS Single Transfer Mode Control Block

In single transfer mode, the PTS control block contains both a source and a destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).

	7											0
Unused		0	0	0		0		0	0		0	0
		7										0
Unused
		0	0	0		0		0	0		0	0
	15											8
PTSDST (H)				PTS Destination Address (high byte)
		7										0
PTSDST (L)				PTS Destination Address (low byte)
		15										8
PTSSRC (H)					PTS Source Address (high byte)
		7										0
PTSSRC (L)
					PTS Source Address (low byte)
		7										0
PTSCON		M2	M1	M0		BW		SU	DU		SI	DI
		7										0
PTSCOUNT				Consecutive Byte or Word Transfers
Register	Location							Function
PTSDST	PTSCB + 4		PTS Destination Address
			Write the destination memory location to this register. A valid address is
			any unreserved memory location within page 00H; however, it must
			point to an even address if word transfers are selected.
PTSSRC	PTSCB + 2		PTS Source Address
			Write the source memory location to this register. A valid address is any
			unreserved memory location within page 00H; however, it must point to
			an even address if word transfers are selected.

Figure 6-24. PTS Control Block — Single Transfer Mode

6-36

								STANDARD AND PTS INTERRUPTS
	PTS Single Transfer Mode Control Block (Continued)
	Register	Location						Function
	PTSCON	PTSCB + 1	PTS Control Bits
			M2:0	PTS Mode
				M2		M1	M0
				1		0	1	single transfer mode
			BW	Byte/Word Transfer
				0	= word transfer
				1	= byte transfer
			SU†	Update PTSSRC
				0	=	reload original PTS source address after each byte or word
						transfer
				1	=	retain current PTS source address after each byte or word
						transfer
			DU†	Update PTSDST
				0	=	reload original PTS destination address after each byte or
						word transfer
				1	=	retain current PTS destination address after each byte or
						word transfer
			SI†	PTSSRC Autoincrement
				0	=	the contents of PTSSRC are not incremented after each
						byte or word transfer
				1	=	the contents of PTSSRC are incremented after each byte
						or word transfer
			DI†	PTSDST Autoincrement
				0	=	the contents of PTSDST are not incremented after each
						byte or word transfer
				1	=	the contents of PTSDST are incremented after each byte or
						word transfer
	PTSCOUNT	PTSCB + 0	Consecutive Word or Byte Transfers
			Defines the number of words or bytes that will be transferred during the
			single transfer routine. Each word or byte transfer is one PTS cycle.
			Maximum value is 255.

†The DU/DI bits and SU/SI bits are paired in single transfer mode. Each pair must be set or cleared together. However, the two pairs, DU/DI and SU/SI, do not need to be equal.

Figure 6-24. PTS Control Block — Single Transfer Mode (Continued)

The PTSCB in Table 6-8 defines nine PTS cycles. Each cycle moves a single word from location 20H to an external memory location. The PTS transfers the first word to location 6000H. Then it increments and updates the destination address and decrements the PTSCOUNT register; it does not increment the source address. When the second cycle begins, the PTS moves a second word from location 20H to location 6002H. When PTSCOUNT equals zero, the PTS will have filled locations 6000–600FH, and an end-of-PTS interrupt is generated.

6-37